Method of manufacturing MOS transistor

Details Method of manufacturing MOS transistor Method of manufacturing MOS transistor

2006-09-12

2006-09-12

Lee, Hsien-Ming (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S514000, C438S522000

Reexamination Certificate

active

07105414

ABSTRACT:
A method of manufacturing a MOS transistor capable of suppressing a short channel effect by suppressing boron (B) ion diffusion in the MOS transistor. The method includes steps of: forming an impurity diffusion suppressing layer in an active region of a semiconductor substrate; forming an impurity layer containing boron ions in a lower portion of the impurity diffusion suppressing layer; and thermally treating on the substrate, wherein the impurity diffusion suppressing layer suppresses diffusion of the boron ions during the thermal treatment step.

REFERENCES:
patent: 6380036 (2002-04-01), Oda et al.
patent: 6475887 (2002-11-01), Kawasaki et al.
patent: 6521527 (2003-02-01), Kuroi et al.
patent: 0 806 796 (1997-11-01), None
patent: 0132441 (1998-09-01), None
Abstract of Korean Patent Publication; Plasma Charge-up Removing Apparatus of a Plasma Enhanced Chemical Vapor Deposition System; Registration No. 20-0132441; Sep. 26, 1998.

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