Method of manufacturing metallic source line, self-aligned conta

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438586, 438790, H01L 218247

Patent

active

056311796

ABSTRACT:
Manufacture of an integrated circuit flash memory devices includes covering a semiconductor substrate with a tunnel oxide layer, a floating gate layer, an intergate dielectric layer, a control gate layer, a silicon dioxide dielectric layer over a silicon nitride layer. Then those layers over the tunnel oxide are patterned into flash memory gate electrode by etching through a source/drain mask followed by ion implanting source/drain dopant ions through the openings formed by etching. Sidewall spacers are formed followed by a dielectric layer through which source line openings are etched down to the source/drain regions. Plug openings are made down to the source/drain regions. An intermetal dielectric layer is deposited comprising PEOX/SOG/PEOX over the device. Then via openings are made over the drain plugs by etching the intermetal dielectric layer through a via mask. Next metal is deposited over the intermetal dielectric layer into the via openings extending down into contact with the drain plugs.

REFERENCES:
patent: 5204286 (1993-04-01), Doan
patent: 5231051 (1993-07-01), Baldi et al.
patent: 5366913 (1994-11-01), Nakao
patent: 5397723 (1995-03-01), Shirota et al.
patent: 5432110 (1995-07-01), Inoue

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