Method of manufacturing low resistance and low junction leakage

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438630, H01L 214763

Patent

active

058997415

ABSTRACT:
A new method of forming an amorphous silicon glue layer in the formation of a contact is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is deposited overlying the semiconductor device structures. An opening is etched through the insulating layer to contact one of the semiconductor device structures. An amorphous silicon layer is deposited overlying the insulating layer and within the opening. Ions are implanted into the amorphous silicon layer whereby grain sizes within the amorphous silicon layer are reduced. Native oxide on the surface of the amorphous silicon layer is removed. A titanium/titanium nitride layer is deposited overlying the amorphous silicon layer. A metal layer is deposited overlying the titanium/titanium nitride layer and filling the opening. The substrate is annealed whereby the titanium layer reacts with the amorphous silicon layer and the silicon semiconductor substrate to form titanium silicide. The metal layer is etched back or patterned to complete metallization in the fabrication of an integrated circuit device.

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patent: 5510296 (1996-04-01), Yen et al.
patent: 5668065 (1997-09-01), Lin
patent: 5700716 (1997-12-01), Sharan et al.

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