Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2006-09-18
2009-10-20
Chu, Chris C (Department: 2815)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S618000, C438S637000, C438S638000, C438S666000, C438S668000, C257SE23145, C257S774000
Reexamination Certificate
active
07605085
ABSTRACT:
First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film22. Dummy vias are formed on the periphery of isolated vias.
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K. Higashi et al., “A Manufacturable Copper/Low-k SIOC/SICN Process Technology for 90nm-node High Performance eDRAM”, Proceedings of the 2002 International Interconnect Technology Conference, pp. 15-17.
Hashimoto Keiji
Iwasaki Akihisa
Matsumoto Susumu
Nishioka Yasutaka
Sekiguchi Mitsuru
Chu Chris C
Leydig , Voit & Mayer, Ltd.
Panasonic Corporation
Renesas Technology Corp.
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