Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-02-15
2011-02-15
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000, C257SE21679
Reexamination Certificate
active
07888211
ABSTRACT:
A method of manufacturing a flash memory device includes preparing a semiconductor substrate comprising a cell area and a peripheral area, forming a first well and an oxide-nitride-oxide (ONO) layer in the cell area, forming a second well in the peripheral area of the semiconductor substrate comprising the first well and forming a first oxide layer in the peripheral area, forming a first polysilicon layer over the ONO layer and the first oxide layer and performing a first etch process to form a memory gate comprising an ONO layer pattern and a first polysilicon pattern in the cell area, forming a second oxide layer pattern and a second polysilicon pattern over either sidewall of the memory gate and forming a gate in the peripheral area, performing a third etch process so that the second oxide layer pattern and the second polysilicon pattern remain over only the one sidewall of the memory gate to form a select gate, and forming a first impurity area in the semiconductor substrate between the memory gates adjacent to each other.
REFERENCES:
patent: 7300833 (2007-11-01), Yamamoto et al.
patent: 2007/0221960 (2007-09-01), Ashida
patent: 10-2006-0103153 (2006-09-01), None
Dongbu Hi-Tek Co., Ltd.
Garber Charles D
Patel Reema
Sherr & Vaughn, PLLC
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