Method of manufacturing flash memory cell

Details Method of manufacturing flash memory cell Method of manufacturing flash memory cell

2000-06-30

2001-08-14

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000

Reexamination Certificate

active

06274418

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a flash memory cell and more particularly to a method of manufacturing a flash memory cell capable of preventing a loss of charges injected into a floating gate thereof.
2. Description of the Prior Art
A principle of data write operation in a flash memory device is to make a program/erase status by applying an appropriate voltage to a source, a drain and a control gate and then charging or discharging electrons to a floating gate, applying an appropriate voltage to a source, a drain and a control gate.
FIG. 1
is a cross-sectional view showing a method of manufacturing a conventional flash memory cell, especially, a stack gate flash memory cell.
A gate oxide layer
11
is formed on a semiconductor substrate
10
, and a polysilicon layer
12
for a floating gate is formed on an entire structure. Then, a patterning process is performed to form the floating gate. Sequentially, a dielectric layer
13
and a polysilicon layer
14
for a control gate are formed on the entire structure. Then, the dielectric layer
13
and the polysilicon layer
14
are patterned by a self-alignment etching process, thereby forming a control gate
14
. Next, a source region S and a drain region D are formed by performing an ion implantation process.
In a program operation of the stack gate flash memory cell, voltages of 9 V and 5 V are applied to the control gate terminal Vg and the drain terminal Vd, respectively. If such voltages are applied, a channel pinch-off phenomenon occurs at the drain, and electrons injected at the source S obtains an energy by moving along a surface channel and passing through a high electric field adjacent to the drain D. Some of hot electrons which are formed by the obtained energy pass beyond a potential barrier and are injected into the floating gate
12
. On the contrary, in an erase operation, voltages of −9 V and 4.3 V are applied to the control gate terminal Vg and the source terminal Vs, respectively. If such voltages are applied, F-N tunneling occurs toward the gate oxide layer
11
of the source which is overlapped with the floating gate, so that the electrons charged in the floating gate
12
are leaked out.
A most important factor determining a reliability of the stack gate flash memory device is data loss fail. That is, the electrons injected into the floating gate leak through various paths to an exterior due to various stimulus such as time, temperature, external bias and the like, so that an original program status is not maintained and the data is lost. Additionally, among the paths, the electron-outflow toward the gate oxide layer of the source is very serious, and therefore, the reliability of the device is degraded.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method of manufacturing a flash memory cell capable of preventing an electron-leakage of a floating gate by forming dividely the floating gate of the flash memory cell into an upper layer and a lower layer about a charge barrier layer.
In order to achieve the above object, a method of forming a flash memory cell in accordance with the present invention comprises the steps of forming a first polysilicon layer on a semiconductor substrate having a gate oxide layer; forming a charge barrier layer on said first polysilicon layer; forming a second polysilicon layer on said charge barrier layer; patterning said second polysilicon layer, said charge barrier layer and said first polysilicon layer, thereby to form a floating gate having said upper polysilicon layer and said lower polysilicon layer divided about said charge barrier layer and forming a dielectric layer and a polysilicon layer for a control gate on an entire structure and patterning said dielectric layer and said polysilicon layer by using a self-alignment etching process thereby to form a control gate.


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