Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-04
2001-08-07
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S267000, C438S304000
Reexamination Certificate
active
06271089
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a flash memory. More particularly, the present invention relates to a method of manufacturing a flash memory having a dual floating gate structure.
2. Description of Related Art
A conventional flash memory is a type of erasable programmable read-only memory (EPROM), which in turn is a type of non-volatile memory. In general, an EPROM cell comprises two gates. One of the gates, known as a floating gate, is fabricated from polysilicon and is used for charge storage. The second gate, known as the control gate, is used for controlling the input and output of data. The floating gate is located beneath the control gate, and is generally in a floating state because there is no connection with external circuits. The control gate is normally wired to the word line. One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, the speed of memory erase is fast, and normally takes just 1 to 2 seconds for the complete removal of a whole block of memory. For most other EPROM, memory erasure can take up to several minutes due to its bit-by-bit operation.
FIG. 1
is schematic, cross-sectional views of a conventional flash memory. The conventional flash memory is constructed with a floating gate transistor. A tunneling oxide layer
102
is formed on a P-type substrate
100
. A floating gate
104
is formed on the tunneling oxide layer
102
and a control gate
108
is formed over the floating gate
104
. A dielectric layer
106
is formed between the floating gate
104
and the control gate
108
and encloses the floating gate
104
. Therefore, the floating gate
104
is electrically isolated from the environment. Additionally, an N-type drain region and an N-type source region
112
are respectively formed in the substrate
100
adjacent to a portion of the substrate
100
beneath the tunneling oxide layer
102
.
Basing on the Flowler-Nordheim effect, during data storage, a voltage of about 8V is applied between the drain region
110
and the source region
112
and a relatively high voltage is applied on the control gate
108
. Hence, the hot electrons flow from the source region
112
into the floating gate
104
and penetrate through the tunneling oxide layer
102
near the drain region
110
. Therefore, the critical voltage of the floating gate transistor is increased and the object of data storage is achieved.
While erasing the data stored in the flash memory, a proper negative voltage is applied on the control gate
108
. Therefore, the electrons captured in the floating gate
108
escape from the floating gate
108
and penetrate through the tunneling oxide layer
102
. After that, the data previously stored in the flash memory are erased and the floating gate transistor is restored to the state before the data were stored in the flash memory.
At this time, each flash memory cell can store only one bit. In order to meets storage requirements, that is, to enlarge the numbers of bits stored in a unit area of a flash memory cell, the typical flash memory manufacturing technique is to increase the numbers of bits stored in the unit area of a flash memory.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing a flash memory having a dual floating gate structure. A substrate is provided. A source/drain region is formed in the substrate. A first conductive layer is formed on the substrate between the source/drain region. A first dielectric layer is located between the substrate and the first conductive layer. A floating gate mask is formed on the substrate and the first conductive layer to expose a portion of the first conductive layer. The portion of the first conductive layer and a portion of the first dielectric layer beneath the exposed conductive layer are removed. The floating gate mask is removed. A conformal second dielectric layer and a second conductive layer are formed over the substrate in sequence. The second conductive layer and the second dielectric layer are formed to respectively form a control gate and a third dielectric layer.
In the present invention, the first conductive layer is separated into two floating gates with the floating gate mask. The source/drain region, the remaining first dielectric layer, the remaining conductive layer, the third dielectric layer and the control gate together form a flash memory having a dual floating gate structure. The remaining conductive layer is transformed into two floating gates. Because each of the floating gates can store one bit, the numbers of bits stored in the unit area is increased. Moreover, the size of the floating gates and the distance therebetween can be adjusted according to the requirements of the product.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5556799 (1996-09-01), Hong
patent: 5612237 (1997-03-01), Ahn
patent: 6103573 (2000-08-01), Harari et al.
Chang Richard
Chen Way-Ming
Charles C.H. Wu & Associates
Chaudhari Chandra
United Microelectronics Corp.
Wu Charles C. H.
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