Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-03-11
2000-04-11
Trinh, Michael
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438257, 438594, H01L 21336
Patent
active
060487682
ABSTRACT:
A method for manufacturing a flash memory. A substrate having a patterned pad oxide layer formed thereon and a patterned mask layer on the pad oxide layer is provided. A doped region is formed in the substrate exposed by the patterned mask layer and the pad oxide layer. A spacer is formed on the sidewall of the patterned mask layer and the pad oxide layer to cover a portion of the doped region. A trench is formed in the substrate exposed by the mask layer and the spacer. An insulating layer is formed to fill the trench, wherein the insulating layer leveled with a top surface of the patterned mask layer. The patterned mask layer and the spacer are removed to respectively expose the patterned oxide layer and the portion of the doped region. A self-aligned tunnel oxide layer is formed on the portion of the doped region. A patterned first conductive layer is formed over the substrate to expose portions of the patterned pad oxide layer above the substrate excluding the doped region. A self-aligned doped region is formed in the substrate under the patterned pad oxide layer exposed by the patterned first conductive layer. A dielectric layer is formed on the patterned first conductive layer and the self-aligned doped region. A patterned second conductive layer is formed over the substrate.
REFERENCES:
patent: 5352619 (1994-10-01), Hong
patent: 5696019 (1997-12-01), Chang
patent: 5780341 (1998-07-01), Ogura
patent: 5851881 (1998-12-01), Lin et al.
patent: 5972752 (1999-10-01), Hong
Ding Yen-Lin
Hong Gary
Trinh Michael
United Semiconductor Copr.
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