Method of manufacturing ferroelectric memory device

Details Method of manufacturing ferroelectric memory device Method of manufacturing ferroelectric memory device

2003-07-16

2004-11-02

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S003000, C438S253000, C438S396000

Reexamination Certificate

active

06812089

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a ferroelectric memory device; and, more particularly, to a method for fabricating the ferroelectric memory capable of preventing a deformation or lift of an electrode by using a heat treatment process.
DESCRIPTION OF RELATED ARTS
A semiconductor memory device using a ferroelectric material as a storage capacitor and a development of the device has been progressed in order to alleviate a refresh problem required to a prior dynamic random access memory (DRAM). A ferroelectric random access memory (FeRAM) device using such a ferroelectric material is one of non volatile memory devices which have such advantages as keeping a stored data maintained even on power-off condition and competing with the prior DRAM device in terms of an operation speed. Accordingly, the FeRAM device is promised to be a next generation memory device.
Such materials as (Bi, La)
4
Ti
3
O
12
(BLT), SrBi
2
Ta
2
O
9
(SBT), SrBi
2
(Ta
1-x
, Nb
x
)
2
O
9
(SBTN), and (Pb, Zr)TiO
3
(PZT) are usually used for forming a film of the ferroelectric material for the FeRAM device. Such a metal as platinum (Pt), iridium (Ir), ruthenium (Ru) or platinum (Pt) having a superior resistance to an oxidation is used for an upper and lower electrode of a storage capacitor at a high heat treatment process for the ferroelectric film formation. A barrier metal layer and a plug for a storage node contact are buried inside an inter layer dielectric film for the purpose of preventing a diffusion between the lower electrode constituted with the metal mentioned above and the plug.
FIG. 1
is a cross-sectional view showing a conventional ferroelectric memory device. As shown, a first inter layer dielectric film
11
is formed on a semiconductor substrate
10
and a tungsten plug
12
for the storage node contact contacting to the semiconductor substrate is formed inside the inter layer dielectric film
11
. The lower electrode
14
is formed over the plug
12
and a predetermined area of the first inter layer dielectric film
11
around the plug
12
. A barrier metal layer
13
buried inside the first inter layer dielectric film is formed between the plug
12
and the lower electrode
14
and a second inter layer dielectric film
15
is formed over the first inter layer dielectric film
11
, wherein the second inter layer dielectric film is laterally arranged to the lower electrode
14
. Herein, an upper surface of the lower electrode
14
should not be covered by the second inter layer dielectric film. Also, a ferroelectric film
16
is formed over the lower electrode
14
and the second inter layer dielectric film
15
. The upper electrode
17
is then formed on the ferroelectric film
16
deposited on the lower electrode
14
. A third inter layer dielectric film
18
is formed over an upper area of the ferroelectric film
16
and a predetermined area of the upper electrode
17
. A wire
19
contacting to an inner side of the third inter layer dielectric film
18
and a predetermined upper area of the upper electrode
18
is formed. Herein, the lower electrode
14
is generally constituted with the metal, i.e., such metal as Pt, Ir, Ru, or Pt and the first, second, and third inter layer dielectric film
11
,
15
and
18
are all formed with a oxide layer. Also, a glue layer constituted with a metal oxide could be formed between the lower electrode
14
and the first inter layer dielectric film
11
, wherein the glue layer is not illustrated and used to improve an adhesion between the lower electrode
14
and the first inter layer dielectric film
11
.
However, in the conventional ferroelectric memory device, since the side wall of the lower electrode
14
is covered by the second inter layer dielectric film, and the lower electrode
14
is subjected to a different thermal expansion rate between the lower electrode
14
metal and the inter layer dielectric films
11
, a strong compressive stress is exerted to the lower electrode
14
at a deposition and heat treatment process for a ferroelectric layer formation
16
. As a result, not only a deformation and lift of the lower electrode
14
but also an exposure and oxidation of the barrier metal layer
13
which are caused by the lift of the lower electrode
14
can occurs. Furthermore, a failure in the storage node contact may happen.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for fabricating a ferroelectric memory device effectively preventing a deformation and lift of a lower electrode caused by a different thermal expansion rate between a lower electrode and a inter layer dielectric film at a succeeding heat treatment process.
In accordance with an aspect of the present invention, there is provided the method for fabricating ferroelectric memory device, including: forming a lower electrode on a predetermined surface of a semiconductor substrate; forming a metal oxide layer over a surface of the lower electrode and a surface of the semiconductor substrate; forming an inter layer dielectric film over the metal oxide layer; performing a blanket etching for the inter layer dielectric film and the metal oxide layer in order to expose an upper surface of the lower electrode; and forming an opening which has a predetermined depth, wherein the opening is obtained by removing only the metal oxide layer between the inter layer dielectric film and the lower electrode through a selective etching process.


REFERENCES:
patent: 5337207 (1994-08-01), Jones et al.
patent: 5566045 (1996-10-01), Summerfelt et al.
patent: 5664989 (1997-09-01), Nakata et al.
patent: 6093575 (2000-07-01), Eguchi
patent: 6576527 (2003-06-01), Nakamura
patent: 6699725 (2004-03-01), Lee
patent: 2002/0109168 (2002-08-01), Kim et al.
patent: 10189912 (1998-07-01), None

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