Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-02-15
2005-02-15
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S309000
Reexamination Certificate
active
06855609
ABSTRACT:
A transistor structure is manufactured for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.
Cai Jun
Hua Guang Ping
Lo Keng Foo
Song Jun
Chartered Semiconductor Manufacturing Ltd.
Ishimaru Mikio
Pham Long
LandOfFree
Method of manufacturing ESD protection structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing ESD protection structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing ESD protection structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3478999