Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-17
2002-03-26
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000
Reexamination Certificate
active
06362047
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the manufacturing of EEPROM memory points including, in a portion of a floating gate, a tunnel-type gate insulator.
2. Discussion of the Related Art
EEPROM memories are formed from memory cells formed, for example, as illustrated in
FIG. 1
, with a read transistor T
1
and a memory point T
2
. Transistor T
1
is a conventional MOS transistor including a drain D
1
, a source S
1
, and an insulated gate G
1
. Memory point T
2
is of double-gate type. It includes a drain D
2
, a source S
2
, and two insulated gates, that is, a floating gate FG and a control gate CG. The invention more particularly address memory points, the floating gate insulator of which includes at least a sufficiently thin portion to enable carriers to flow by tunnel effect between the underlying channel and the floating gate, said insulator being called a “tunnel insulator” or “tunnel oxide”. Source S
1
of transistor T
1
is interconnected to drain D
2
of memory point T
2
.
FIGS. 2A
,
2
B, and
2
C respectively illustrate a top view and cross-section views along respective axes B—B and C—C of a conventional memory cell.
The cell is formed in an active region of a semiconductor substrate
1
, typically made of polysilicon, laterally delimited by field insulation areas
2
.
An insulating layer
3
is intended for forming the gate insulator of transistor T
1
and the non-tunnel portion of the insulator of floating gate FG of memory point T
2
. Insulator
3
generally is a silicon oxide layer (SiO
2
) deposited by vapor-phase chemical deposition.
Layer
3
has been partially removed from the surface of the active region, to form in the areas corresponding to memory point T
2
a window W, the contour of which is illustrated, in top view, in dotted lines in
FIG. 2A
, and the width Ww and the length W
1
of which respectively appear in
FIGS. 2B and 2C
. Window W extends across the entire width of the active region, to field insulation areas
2
and thereabove. An insulating layer
4
has been formed by thermal oxidation of the exposed surface of substrate I at the bottom of window W. Layer
4
forms a tunnel oxide area of the insulator of floating gate FG of memory point T
2
.
A conductive layer
5
covers insulating layers
3
and
4
and a portion of areas
2
. Typically made of polysilicon of a 150-nm thickness, layer
5
is etched to form floating gate FG of memory point T
2
and at least a portion of gate G
1
of the transistor.
An insulating layer
6
covers layer
5
. Typically a silicon oxide—silicon nitride (Si
3
N
4
)—silicon oxide (ONO) multilayer of a thickness between 210 and 230 nm, layer
6
is intended for forming the insulator of control gate CG of memory point T
2
.
Finally, a conductive layer
7
covers layer
6
. Typically made of in-situ doped polysilicon of a thickness between 400 and 500 nm, generally 450 nm, layer
7
is essentially intended for forming control gate CG. To form gate G
1
, the corresponding portions of layers
5
and
7
are then electrically connected.
A disadvantage of the obtained structure is the fragility of the tunnel oxide at the level of border regions OP
1
, OP
2
between the active region and areas
2
(FIGS.
2
A and
2
C). Indeed, in these border regions, the growth of tunnel oxide
4
will, in practice, be irregular and will exhibit a smaller thickness. This causes risks of occurrence of leakage currents due to a local “piercing” of the insulator. A short-circuit may even occur between floating gate FG and underlying substrate
1
.
Another disadvantage of such a forming method is the irregularity of length W
1
of the tunnel oxide. Indeed, if width Ww of the tunnel oxide is defined by the etch mask of layer
3
(opening of window W), its length W
1
is defined by the width of the active region between layers
2
. In practice, the “bird's beak” ends of areas
2
are irregular. The length, and thus the surface area of insulator
4
, are then poorly defined and may vary from one memory cell to another. This surface area can be insufficient or excessive and result in malfunctions of the device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a novel method for manufacturing a novel memory cell structure that does not exhibit the above-mentioned defects.
To achieve these and other objects, the present invention provides a method for manufacturing a memory point including a control gate and a floating gate above an insulator including a sufficiently thin area to enable a tunnel effect between an underlying semiconductor substrate and the floating gate, including the steps of:
delimiting at the surface of the substrate an active region by field insulation areas;
forming a first insulating layer;
opening a window in the first insulating layer to partially expose the entire width of the active region and a portion of the insulating areas;
forming a second very thin insulating layer by thermal oxidation;
depositing a first conductive material;
forming a third insulating layer; and
depositing a second conductive material, and further including the step of etching the second conductive material, the third insulating layer, the first conductive material and the second and first insulating layers according to a same contour to expose the active region and the insulation areas in the vicinity of the border regions between the active region and the insulation areas.
According to an embodiment of the present invention, the step of etching the second conductive material, the third insulating layer, the first conductive material and the second and first insulating layers enables defining the gate structure of a read transistor of an EEPROM-type memory cell including said memory point.
According to an embodiment of the present invention, the window is rectangular.
According to an embodiment of the present invention, the window has dimensions of 0.7* 1.2 &mgr;m.
According to an embodiment of the present invention, the first insulating layer is a silicon oxide layer of a thickness ranging between 20 and 30 nm.
According to an embodiment of the present invention, the thermal oxide has a thickness between 5 and 10 nm.
According to an embodiment of the present invention, the first conductive material is a polysilicon layer of a 150-nm thickness.
According to an embodiment of the present invention, the second conductive material is a polysilicon layer of a thickness between 400 and 500 nm.
According to an embodiment of the present invention, after depositing the second conductive material, the surface of the second conductive material is silicided.
According to an embodiment of the present invention, the second conductive material is a polysilicon and tungsten silicide multilayer.
The foregoing as well as other objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of an embodiment of the present invention in connection with the accompanying drawings.
REFERENCES:
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patent: 5256584 (1993-10-01), Hartmann
patent: 5336628 (1994-08-01), Hartmann
patent: 5511036 (1996-04-01), Farb et al.
patent: 5596529 (1997-01-01), Noda et al.
patent: 5702966 (1997-12-01), Noda et al.
patent: 5702988 (1997-12-01), Liang
patent: 5844268 (1998-12-01), Noda et al.
patent: 5895240 (1999-04-01), Chuang et al.
French Preliminary Search Report from French patent application No. 9913378, filed Oct. 21, 1999.
Dang Phuc T.
Morris James H.
Nelms David
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
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