Method of manufacturing DRAM capacitor

Details Method of manufacturing DRAM capacitor Method of manufacturing DRAM capacitor

2000-07-17

2002-03-05

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S672000, C438S675000

Reexamination Certificate

active

06352896

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89111023, filed Jun. 7, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing semiconductors. More particularly, the present invention relates to a method of manufacturing the capacitor of deep sub-micron dynamic random access memory (DRAM).
2. Description of Related Art
DRAM is a widely used integrated circuit device in semiconductors, especially in the telecommunications industry. Hence, it is a common goal in the electronic industry to develop a DRAM that has a higher memory capacity through device miniaturization. However, how to retain original quality and reliability despite miniaturization is a difficult technical problem that needs to be solved.
The memory cell array of a conventional stack-type DRAM generally includes at least an active area (AA), a word line (WL), a patterned self-aligned contact (SAC), a patterned bit line contact (BLC), a patterned bit line (BL) and a node contact. Altogether, six optical masks are required to form all the relevant structures.
FIG. 1
is a schematic cross-sectional view showing a conventional stack-type capacitor over a bit line (COB) DRAM. As shown in
FIG. 1
, an active region
104
is marked out of a substrate
100
by an isolation structure
102
. The COB DRAM also includes word lines
106
, bit lines
108
and a capacitor
110
. The bit lines
108
are electrically connected to the substrate
100
through a self-aligned contact
112
. Similarly, the capacitor
110
is electrically connected to the substrate
100
through a node contact
114
. The word line
106
, the bit line
108
and the capacitor
110
are electrically insulated from each other by dielectric layers
116
.
The six masking operations includes: a mask for forming an island pattern in the active region
104
, two masks for forming the word lines
106
and the line/space pattern, three masks for forming the contact hole pattern of the self-aligned contact
112
, the bit line contact and the node contact
114
. As dimensions of each DRAM device shrinks, design rules for fabricating the devices become more restrictive. Hence, electrical contacts become harder to produce.
In addition, the amount of overlap and the alignment between different photomasks have to be increasingly accurate. Thus, the process window for forming a stack-type DRAM is limited.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of manufacturing a DRAM capacitor capable of improving the process window and overlay margin.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A first plug and a second plug are formed between the word lines in locations for forming the desired bit line contact and the node contact, respectively. Insulation material is deposited into the remaining space between the word lines. A bit line contact is formed above the first plug. Next, a plurality of parallel bit lines is formed above the substrate, and the bit lines are perpendicular to the word lines. The bit lines, which are electrically insulated from each other, are electrically connected to the substrate through the bit line contact and the first plug. Furthermore, each bit line is covered on top by a hard material layer. Finally, a node contact is formed over the second plug.
This invention also provides an alternative method of manufacturing a DRAM capacitor. An active region is marked out in a substrate. A plurality of mutually parallel word lines is formed over the substrate. The word lines are separated from each other by spaces. Insulation material is deposited into the space between the word lines to form a first insulation layer. The first insulation layer is patterned to form a first self-aligned contact opening for forming the bit line contact and a second self-aligned contact opening for forming the node contact. Conductive material is deposited into the first and the second self-aligned contact opening to form a first self-aligned contact and a second self-aligned contact, respectively. A second insulation layer is formed over the word lines. The second insulation layer is patterned to form a bit line contact opening. Conductive material is again deposited into the bit line contact opening to form a bit line contact. Hence, the bit line contact is electrically connected to the substrate via the first self-aligned contact. In the subsequent step, a dielectric layer is formed over the second insulation layer. The dielectric layer is patterned to form a plurality of parallel trenches running perpendicular to the word lines. Conductive material is deposited into the trenches to form bit lines. The upper surface of the bit lines is lower than the upper surface of the dielectric layer. In addition, the bit line is electrically connected to the first self-aligned contact via the bit line contact. A hard material layer is formed over the bit lines that fill the remaining space of the trenches. The dielectric layer and the second insulation layer are patterned to form a node contact opening. Conductive material is deposited into the node contact opening to form a node contact. The node contact is electrically connected to the substrate via the second self-aligned contact.
In this invention, the self-aligned contacts and the node contacts are formed by a self-aligned process. Hence, both the process window and the overlay margin improve.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5998225 (1999-12-01), Crenshaw et al.

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