Method of manufacturing CMOS with silicide contacts

Details Method of manufacturing CMOS with silicide contacts Method of manufacturing CMOS with silicide contacts

2008-04-08

2008-04-08

Pert, Evan (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

10701435

ABSTRACT:
A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the insulation film, a first metal silicide layer formed on the bottom of the first contact hole, the first metal silicide layer being provided by a reaction of the n-channel impurity diffused region of the n-channel MISFET with a first metal, a second contact hole formed in the insulation film, a second metal silicide layer formed on the bottom of the second contact hole, the second metal silicide layer being provided by a reaction of the p-channel impurity diffused region of the p-channel MISFET with a second metal, and a work function of the second metal silicide layer being higher than that of the first metal silicide layer.

REFERENCES:
patent: 5202275 (1993-04-01), Sugiura et al.
patent: 6465887 (2002-10-01), Chu et al.
patent: 11-214650 (1999-08-01), None
patent: 2000-286411 (2000-10-01), None
patent: 2001-250792 (2001-09-01), None
patent: 2002-094058 (2002-03-01), None
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Notification of Reasons for Rejection dated Apr. 22, 2005, issued by the Japanese Patent Office in counterpart Japenese Application No. 2002-323493.

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