Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-28
2003-08-12
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S248000, C438S386000, C438S387000, C438S391000
Reexamination Certificate
active
06605504
ABSTRACT:
BACKGROUND OF THE INVENTION
Semiconductor devices are employed in many types of equipment to perform a wide variety of applications. An important type of semiconductor device for use in the memory field is known as dynamic random access memory (“DRAM”). DRAM is extensively used for memory in computers. A basic DRAM cell may include a capacitor and a transistor formed in a semiconductor substrate. The capacitor stores a charge representing data. The transistor allows the data to be refreshed, read from, or written to the capacitor. By reducing the surface area of the capacitor or the transistor, more DRAM cells can fit onto a chip. The increase in the amount of DRAM cells results in greater memory capacity for the chip.
One method of minimizing the surface area of a DRAM cell or other memory cell is to vertically construct the components (i.e., where a semiconductor device includes components formed at several or more layers thereof). One way to accomplish such vertical construction may involve forming a trench in a semiconductor substrate. For example, polysilicon (“poly-Si”) may be deposited in the trench. A recess may be created in the poly-Si by removing a portion of the poly-Si through an etching process. Layers of conductive, semiconductive and/or insulating material can then be deposited in the recessed area of the poly-Si. The steps of etching the poly-Si and depositing new material can be repeated until the desired components are formed.
A compact DRAM cell can be formed by stacking the capacitor and the transistor within the trench. For instance, the trench may be etched or otherwise formed in the substrate. The capacitor may be formed in the bottom portion of the trench. Next, an isolation material such as a trench top oxide (“TTO”) may be formed over the capacitor. Adjacent to the TTO is a “buried strap.” The transistor is formed on top of the TTO and the buried strap. The TTO isolates the transistor gate from the capacitor. The buried strap is the contact between the transistor and the capacitor and comprises a material such as doped polysilicon. The dopant may be arsenic, phosphorous, boron or another suitable material. The buried strap may also act as the source or drain of the transistor.
Such stacked memory devices (“vertical memory cells”) can occupy less surface area compared to planar memory cells (e.g., where the transistor and capacitor are side by side) or diagonal memory cells (e.g., where the capacitor is formed in the trench and the transistor is adjacent to the surface of the trench). Thus, vertical memory cells may be placed very close together. While increasing the memory cell density, and hence increasing the memory capacity of a chip, the closeness of vertical memory cells may be problematic.
Closely spaced vertical memory cells may interfere with each other because the dopant of the buried strap tends to diffuse out into the substrate. Typically, diffusion occurs in both vertical and horizontal directions. Vertical diffusion (e.g., diffusion in a direction parallel to the sidewalls of the trench) may improve the contact between the transistor and the capacitor of one vertical memory cell. However, when the dopant from one vertical memory cell diffuses horizontally into the substrate (e.g, diffusion in a direction perpendicular to the sidewalls of the trench), the dopant may come into contact either with the diffused dopant from a nearby vertical memory cell or a portion of the nearby cell itself. This contact may create “cross-talk” between the transistors of the nearby vertical memory cells. Cross-talk occurs when a signal from one device is inadvertently received by another device. In this situation, cross-talk may interfere with a transistor's ability to read to or write data from the capacitor to which it is attached, rendering one or both vertical memory cells nonfunctional. Therefore, there is a need for vertical memory cells having minimized buried strap horizontal out-diffusion.
SUMMARY OF THE INVENTION
The present invention provides a buried strap with reduced out-diffusion for use in stacked memory cells and a method of fabricating the buried strap.
In accordance with an embodiment of the present invention, a semiconductor device comprises a semiconductor substrate with a trench formed therein. The trench includes a sidewall. A capacitor is formed in the trench. The capacitor includes a node dielectric lining a portion of the sidewall. A buried plate is disposed in the semiconductor substrate adjacent to the node dielectric. Capacitor fill material is disposed within the trench. An insulator is disposed over at least a part of the capacitor fill material. The semiconductor device also includes a transistor, which has a source, a gate and a drain formed of a buried strap. The gate is disposed at least partly over the insulator and connects to the source. The buried strap is adjacent to the insulator and acts to connect the gate to the capacitor fill material. The buried strap includes a liner and a strap fill material. The liner reduces diffusion of the dopant in a direction substantially perpendicular to the sidewall while allowing diffusion of the dopant in a direction substantially parallel to the sidewall. Preferably, the liner is at least 22 Å thick.
In accordance with another embodiment, a semiconductor device includes a trench formed in a semiconductor substrate. The trench has a sidewall defining lower, middle and upper regions. The semiconductor device also includes a capacitor. The capacitor has a capacitor fill material comprising polysilicon and a dopant. The fill material is formed within the lower and middle regions of the trench. The semiconductor device also includes a transistor partly disposed within the upper region of the trench. An insulator is disposed on top of the capacitor. The insulator is operable to provide isolation between the capacitor and the transistor. The semiconductor device also includes a buried strap. The buried strap includes a nitride liner and a strap fill material. The buried strap is operable to function as a drain of the transistor and is operable to connect the transistor to the capacitor. The nitride liner prevents diffusion of the dopant in a direction substantially perpendicular to the sidewall. Preferably, the buried strap is formed within a divot disposed proximate to the insulator, the capacitor fill material and the sidewall.
A method of fabricating a semiconductor device of the present invention may comprise forming a trench in a semiconductor substrate, forming a collar along a sidewall of the trench, and forming a capacitor. The capacitor includes a capacitor fill material having a dopant. The capacitor fill material is formed in a region of the trench. The collar may be recessed to form a divot, wherein a top portion of the collar is below a top surface of the capacitor fill material. A buried strap may be formed within the divot. The dopant is operable to diffuse in a direction substantially parallel to the sidewall. Preferably the liner has a first side disposed adjacent to the sidewall and a bottom connected to the first side and disposed over the top portion of the collar.
Another method of fabricating a semiconductor device of the present invention may comprise forming a trench in the semiconductor substrate. The trench has a sidewall defining lower, middle and upper regions. The method forms a node dielectric along the sidewall in the lower region of the trench. A collar is formed along the sidewall in the middle and upper regions of the trench. The lower and middle regions are substantially filled with a capacitor fill material, which comprises polysilicon and a dopant. The capacitor fill material has a top surface. A top portion of the collar is etched below the top surface of the capacitor fill material to form a divot. A nitride liner is deposited within the divot. The nitride liner has a thickness of at least about 22 Å. A strap fill material is formed within the nitride liner. The strap fill material and the nitride liner form a buried strap. The nitri
JaiPrakash Venkatachalam C.
Ranade Rajiv
Brewster William M.
Chaudhuri Olik
Infineon - Technologies AG
Lerner David Littenberg Krumholz & Mentlik LLP
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