Method of manufacturing bit lines in memory

Details Method of manufacturing bit lines in memory Method of manufacturing bit lines in memory

1999-05-17

2001-03-20

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000

Reexamination Certificate

active

06204127

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88106720, filed Apr. 27, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing mask read-only-memory (ROM). More particularly, the present invention relates to a method that uses a damascene process to manufacture the bit lines of a mask ROM.
2. Description of Related Art
The bit lines of most flat cell mask ROM are formed by implanting ions into a substrate to form a buried layer. However, as the level of integration increases, resistance of these buried bit lines also increases, and hence the ultimate operation speed of the mask ROM is limited. The reason for this is that even by doping the substrate with the highest possible concentration of N-type ions, the ultimate resistivity can only reduced to about 70 to 80 &OHgr;/□. If, for the sake of decreasing the resistivity of the buried lines, the ion concentration in the doping operation is further increased, punch through between neighboring memory cell bit lines may happen.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing the bit lines of ROM. The method includes the steps of forming a protective layer and a mask layer sequentially over a substrate, and then patterning the mask layer to form an opening that exposes a portion of the protective layer. Thereafter, spacers are formed on the sidewalls of the opening, and then a portion of the protective layer and the substrate areas exposed by the opening are removed in sequence to form a trench in the substrate. Next, the mask layer, the spacers and the protective layer are all removed. Finally, conductive material is deposited into the trench to form a bit line.
Since bit lines are formed using a damascene method instead of the conventional ion implant method, resistivity of bit lines can be lowered and operating speed of devices can be increased. Moreover, resistivity of a bit line can be decreased by forming a deeper trench. In addition, spacer structures can be used to reduce the outer diameter of the opening so that a trench with a narrower opening can be formed in the substrate. Hence, the ultimate resolution of photolithographic processing operation is relieved, and level of device integration can be further increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5830797 (1998-11-01), Cleeves
patent: 6027982 (2000-02-01), Peidous et al.
patent: 6040218 (2000-03-01), Lam
patent: 6051469 (2000-04-01), Sheu et al.
patent: 6060399 (2000-05-01), Kim et al.

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