Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-19
2001-01-09
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S341000, C438S363000, C438S234000
Reexamination Certificate
active
06171894
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacturing of integrated circuits, and more specifically of so-called BICMOS circuits, that is, circuits including bipolar transistors and complementary MOS transistors.
2. Discussion of the Related Art
In such structures, interest is generally more specifically focused on the quality of the NPN-type bipolar transistors, PNP transistors being by nature slower than NPN transistors. The NPN transistors must always be of good quality. A first and a second category of BICMOS integrated circuits are however distinguished. In the first category, the performance of the bipolar NPN transistors, which must enable operating at frequencies likely to reach a few gigahertz are essentially stressed. In the second category, the circuits include MOS transistors essentially performing the logic functions and bipolar transistors essentially intended for the input/output amplifiers and the implementation of a few analog functions. This latter case, in which the major part of an integrated circuit is formed by CMOS transistors and where the NPN bipolar transistors must be of fine quality without necessarily have to operate at very high frequencies on the order of one gigahertz will be considered herein.
FIG. 1
is a simplified cross-section view of a portion of a conventional BICMOS integrated circuit. The left-hand portion of the drawing includes a P-channel MOS transistor (PMOS), the center portion of the drawing contains an N-channel MOS transistor (NMOS) and the right-hand portion of the drawing contains an NPN-type bipolar transistor. The structure is formed from a single-crystal silicon wafer
10
of type P on which is formed an N-type epitaxied layer. Buried layers are formed at the interface between the silicon substrate and the epitaxial layer.
The P-channel MOS transistor is formed in an N-type well
11
(Nwell), preferably formed above a heavily-doped N-type layer
12
, itself formed at the upper portion of substrate
10
. The N well is delimited laterally and in surface by insulating areas, for example, a thick oxide
14
formed by so-called LOCOS techniques. Another thick oxide region
15
delimits a portion of N well
11
. In the main portion of the N well is formed a P-channel MOS transistor including, on either side of a gate
16
, drain and source regions D and S. Conventionally, this structure includes spacers and drain and source extension areas of low doping level (LDD). A heavily-doped N-type area
17
in the portion of the N well delimited by thick oxide
15
enables contacting the well.
The N-channel MOS transistor is formed complementarily in a P-type well
21
(Pwell) formed on a buried layer
22
. The P well is delimited by a thick oxide
24
and a thick oxide
25
delimits a portion of the well. The N-channel transistor is formed in the main portion of the well on either side of an insulated gate
26
. A heavily-doped P-type contact
27
enables connecting the P well.
The NPN-type bipolar transistor is formed in an area
31
of the N-type epitaxial layer located above a heavily-doped N-type buried layer
32
. Region
31
corresponds to the collector and region
32
corresponds to a collector contact area which is connected to the surface of the integrated circuit via a heavily-doped N-type collector well
33
. A base area
34
is formed by implantation and/or diffusion at the surface of the N-type epitaxial layer. Above this base region, a heavily-doped N-type polysilicon layer
35
enables creating, by diffusion, an emitter region
36
in base
34
. A heavily-doped P-type area
37
is arranged laterally with respect to intrinsic base region
34
, for example, as shown in the drawing and enables a base contact recovery. Further, N-type epitaxial layer portion
31
in which the bipolar transistor is formed must be isolated from the other components of the structure formed in the N-type epitaxial layer or in an N-type well. Thus, N-type region
31
must be surrounded with a P-type well. This P-type well may correspond, as shown to the left of the bipolar transistor, to a well in which is formed an N-channel MOS transistor or else, as shown by region
38
to the right of the drain, to a specific insulating wall
38
corresponding to a diffusion performed at the same time as the P-type wells.
A method of manufacturing the structure illustrated in
FIG. 1
made on a P-type substrate (
10
) includes the following main steps:
implanting the N-type buried regions (
12
,
32
);
implanting the P-type buried regions (
22
);
growing an epitaxial layer having for example a thickness on the order of 1 &mgr;m and a doping level on the order of 10
16
atoms/cm
3
;
forming the thick insulating oxide regions (
14
,
15
,
24
,
25
);
implanting the N wells (
11
);
implanting the collector wells (
33
);
implanting the P wells (
21
) (and P insulating regions
38
);
forming the gates of the N-channel and P-channel field effect transistors;
implanting the N-type lightly-doped regions (LDD), then implanting the P-type lightly-doped regions (LDD)—each time, simultaneously implanting the contact region of the well other than that in which the LDD source and drain implantations are performed; (for the following operations, the MOS transistor regions are masked and the bipolar transistors are formed)
implanting a P-type base region (
34
) in the epitaxial area (
31
);
masking an emitter region and depositing a heavily-doped N-type polysilicon layer (
35
);
delimiting the emitter contact layer (
35
);
forming the gate spacers of the MOS transistors and lateral spacers around the emitter contact polysilicon area; (for the following operations, the MOS transistor and bipolar transistor regions are both processed)
implanting the N-type drain-source regions of the N-channel transistors, the contact region with the N wells, and the collector contact region;
implanting the P-type drain-source regions of the P-channel transistors, the contact region with the P well, and the base contact region.
This method of manufacturing, in the same semiconductor substrate, complementary MOS transistors and bipolar transistors has, in particular, the following differences with a conventional method of manufacturing an integrated circuit only including complementary MOS transistors:
an N-type epitaxy on a P-type substrate is used, while a conventional method of CMOS transistor manufacturing uses a lightly-doped P-type epitaxy on a more heavily-doped P-type substrate;
the forming of the epitaxial layer is preceded by the forming of buried layers;
there is a specific deep doping step to form the collector wells.
Thus, as compared to a conventional method of CMOS transistor manufacturing, the method described hereabove of manufacturing a BICMOS transistor essentially has the disadvantage of requiring the forming of buried layers before forming an epitaxial layer. This considerably increases the manufacturing duration and costs. Indeed, it is more difficult, due to exodiffusion problems, to form an epitaxial layer on a inhomogeneous substrate including N
+
and P
+
regions than on a homogeneous substrate. Further, silicon manufacturers provide homogeneous substrates with an epitaxied layer, and since they manufacture such elements in large series, the costs are very competitive.
This complication of the manufacturing method is due to the fact that it is desired, for a bipolar transistor, to have in the vicinity of the base, a lightly-doped N-type collector region. Indeed, this light doping of the collector in the vicinity of its base helps to provide high gain and good voltage breakdown characteristics to a transistor. However, the lightly-doped collector region must not be too extensive to limit the resistance of access to the collector. Essentially due to these two considerations, integrated circuit NPN transistors almost systematically include N
+
-type buried layers under an N-type epitaxy, the buried layer being used as a lightly resistive access to a lightly-doped collector.
SUMMARY OF THE INVENTION
Thus, a
Dang Trung
Galanthay Theodore E.
Morris James H.
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
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