Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2001-04-13
2003-09-23
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S771000, C438S778000, C438S793000
Reexamination Certificate
active
06624094
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing an interlayer dielectric film using vacuum ultraviolet CVD.
2. Description of the Related Art
Conventional interlayer dielectric films for use in DRAMS and Logic LSIs are formed by a plasma CVD, a thermal CVD, an oxide, and an 0
3
-CVD by using TEOS (tetra ethyl ortho silicate) as a material gas or source gas.
The aforementioned methods involve thermal treatment at a temperature higher than 700° C. when an interlayer dielectric film is formed by thermal CVD, and at a temperature higher than 350° C. when an interlayer dielectric film is formed by plasma CVD.
In addition, plasma discharge occurs when plasma CVD is used. Thermal treatment at high temperature and plasma damage the elements that form an insulating film. With increasing micro fabrication and multi-layered wiring of semiconductor devices, the adverse effects of the conventional method cannot be ignored in manufacturing reliable semiconductor devices. When an interlayer dielectric film is formed by thermal CVD or plasma CVD, the interlayer dielectric film is configured to the stepped structure immediately below the interlayer dielectric film, so that the resulting interlayer dielectric does not have a good step coverage effect as required of an interlayer dielectric film.
SUMMARY OF THE INVENTION
The present invention was made in view of the aforementioned drawbacks of the conventional art.
An object of the invention is to provide a vacuum ultraviolet CVD method of forming a flat interlayer dielectric film and having a good step coverage, in which method the interlayer dielectric film is formed at a temperature lower than 350° C. by using an organic source such as TEOS (tetra ethyl ortho silicate) that contains silicon therein.
A method of manufacturing an interlayer dielectric film having a flat top surface and a good step coverage effect by a vacuum ultraviolet CVD, the method comprising the steps of:
placing a wafer in a vacuum chamber having a window;
causing a first gas or source gas that contains silicon to flow through the vacuum chamber;
exposing the wafer to light emitted from an excimer lamp through the window; and
maintaining an atmosphere in the chamber at a temperature lower than 350° C. to form an SiOCH film on the wafer.
The method may further include adding a second gas or additional gas to the first gas, the second gas containing oxygen atoms therein.
The method may further include elevating a temperature of atmosphere in the chamber with the film remaining in the chamber after forming the film in an environment of the first and second gases.
The method may further include stopping supplying oxygen after forming the film in an environment of the first and second gases and then further forming the film in the environment of TEOS alone.
The method may, further include maintaining the wafer at a temperature in the range from 25 to 350° C. when the film is formed after forming the film in an environment of the first and second gases.
The method further includes:
adding a second gas to the first gas, the additional gas containing oxygen atoms therein;
stopping supplying oxygen to the chamber after a certain length of time; and
elevating the film in the chamber to be exposed to vacuum ultraviolet.
The method further includes:
adding a second gas to the first gas, the second gas containing oxygen atoms therein;
stopping supplying the second gas to chamber after a certain length of time; and
elevating temperature of atmosphere in the chamber with the film remaining in the chamber to be exposed to vacuum ultraviolet while the temperature is being elevated.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific example, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 5387546 (1995-02-01), Maeda et al.
patent: 5698472 (1997-12-01), Harris
patent: 63-105970 (1988-05-01), None
patent: 06-097158 (1994-08-01), None
patent: 2001-274155 (2001-05-01), None
Ichiki Yutaka
Miyano Jun-ichi
Motokawa Yousuke
Motoyama Yoshikazu
Toshikawa Kiyohiko
Frank Robert J.
Huynh Yennhu B
Jr. Carl Whitehead
Oki Electric Industry Co. Ltd.
Venable LLP
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