Method of manufacturing an integrated circuit with MOS transisto

Details Method of manufacturing an integrated circuit with MOS transisto Method of manufacturing an integrated circuit with MOS transisto

1998-04-27

2000-02-22

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438210, 438382, H01L 218234

Patent

active

060279656

ABSTRACT:
The method described provides for the formation of an implantation mask of polycrystalline silicon comprising strips for providing the gate electrodes of the MOS transistors and portions defining openings for the formation of resistors. The method further includes low-dose ionic implantation through the implantation mask to form pairs of regions at the sides of the gate strips and resistive regions through the openings, the formation of an insulating layer on the entire structure thus produced, and anisotropic etching of the insulating layer so as to uncover the areas of the substrate not covered by the polycrystalline silicon mask, but leaving a residue of insulating material along the edges of the gate strips. To compensate for the removal of a surface layer from the resistive regions due to the anisotropic etching, a second low-dose implantation is carried out without masking of the substrate, with a dose and an energy such as to produce a predetermined resistivity for the resistive regions without altering the resistivities of the source and drain regions of the MOS transistors.

REFERENCES:
patent: 4416055 (1983-11-01), Mac Carthy et al.
patent: 4418469 (1983-12-01), Fujita
patent: 4830976 (1989-05-01), Morris et al.
patent: 5668037 (1997-09-01), Prall et al.
Patent Abstracts of Japan, vol. 006, No. 009 (E-090), Jan. 20, 1982 and JP 56 130960A (Fujitsu Ltd), Oct. 14, 1981.
Patent Abstracts of Japan, vol. 009, No. 081 (E-307), Apr. 10, 1985 and JP 59 214250A (Toshiba KK), Dec. 4, 1984.

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