Method of manufacturing an insulated gate type semiconductor...

Details Method of manufacturing an insulated gate type semiconductor... Method of manufacturing an insulated gate type semiconductor...

1999-10-01

2001-02-27

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S273000, C257S330000

Reexamination Certificate

active

06194273

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an insulated-gate type semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
FIG. 1
shows a conventional MOSFET having a U-shaped groove. In
FIG. 1
, the reference number
1
represents a semiconductor body including an n
+
type semiconductor substrate
2
, and an epitaxial layer
4
provided on the semiconductor substrate
2
and formed, on its surface, with a plurality of U-shaped grooves
3
(only one of them is illustrated). The epitaxial layer
4
includes an n
−
type drain region
5
which is an initial layer of the epitaxial layer
4
, a p type base region
6
provided on the drain region
5
, and an n
+
type source region
7
provided on a surface of the base region
6
. The groove
3
is formed such that it penetrates the base region
6
from the surface of the source region
7
and reaches the drain region
5
, and a crystal plane of the side wall surface of the groove
3
is substantially {100} plane. A gate oxide film
8
is provided on an inner surface of the groove
3
and a groove shoulder
3
a
, and a polysilicon gate electrode
9
is provided on the gate oxide film
8
. An interlayer insulation film
10
is provided on the epitaxial layer
4
such as to cover the gate electrode
9
, and a source electrode
11
is provided on the interlayer insulation film
10
for electrically connecting with the source region
7
and a surface of the base region
6
by Ohmic contact. Although it is not illustrated, a gate wire is provided on the source electrode
11
through an interlayer insulation film for electrically connecting with the gate electrode
9
.
Next, a manufacturing method of this MOSFET will be explained.
FIGS. 2A
to
2
C are sectional views showing the manufacturing method in the order of steps.
First, as shown in
FIG. 2A
, the initial layer of the epitaxial layer is formed on the n
+
type semiconductor substrate
2
in which a crystal plane of the substrate surface is (100) plane and a crystal plane of an orientation flat is (0{overscore (1)}{overscore (1)}). Then, a silicon oxide film
12
is formed on a surface of the initial layer by thermal oxidation, a silicon nitride film
13
which functions as a mask for preventing the oxide film from growing is allowed to grow on the silicon oxide film
13
by CVD process. Thereafter, the nitride film
13
, the oxide film
12
and the initial layer are selectively subjected to etching by PR and dry etching, thereby forming an n
−
type epitaxial layer
4
a in which a plurality of initial grooves
14
(only one of them is illustrated). The initial groove
14
is subjected to etching such that the crystal plane of the side wall surface becomes substantially {110}. During PR, the adjustment of alignment of patterns are carried out horizontally and vertically with respect to the orientation flat.
Next, as shown in
FIG. 2B
, the initial groove
14
is thermal oxidized using the nitride film
13
as a mask, and with this oxidization, an LOCOS oxide film
15
is formed and the initial groove
14
becomes the U-shaped groove
3
. Then, the nitride film
13
is removed from the entire surface by wet etching process, and boron is injected by ion implantation and thermally diffused using the LOCOS oxide film
15
as a mask, thereby forming the P type base region
6
. Further, the base region
6
is masked by the LOCOS oxide film
15
and a photoresist film by PR, arsenic is injected by ion implantation, the photoresist is removed and then is thermally diffused, thereby forming the n
+
type source region
7
. As a result, the epitaxial layer
4
a shown in region
7
. As a result, the epitaxial layer
4
a
shown in drain region
5
which is the initial layer of the epitaxial layer on which the grooves
3
are formed, the base region
6
, and the source region
7
.
Next, as shown in
FIG. 2C
, the LOCOS oxide film
15
and the oxide film
12
are removed by the wet etching process so that the base region
6
, the source region
7
and the inner surface of the groove
3
are exposed. Then, the gate oxide film
8
is formed on the inner surface of the groove
3
, the base region
6
and the source region
7
by the thermal oxidization process, and the surface of the epitaxial layer
4
subjected to the above-described steps is covered with the polysilicon film
16
by the CVD process.
FIG. 1
is a sectional view showing the device after the above-described third step. Subsequently, in a fourth step, the gate electrode
9
is formed by patterning the polysilicon film
16
with PR(Photolithography) and dry etching processes remaining a portion of the film
16
on the grooves
3
and a part of the source region
7
. Then, the surface of the epitaxial layer
4
is covered with the interlayer insulation film
10
by the CVD process. Then, a contact hole is formed in the interlayer insulation film
10
and the gate oxide film
8
such that the portion of the surface of the source region
7
and the surface of the base region
6
are exposed. After that, the surface of the epitaxial layer
4
subjected to the above-described steps is covered with an aluminum film by sputtering process, and the aluminum film is selectively removed by PR and the dry etching process, thereby forming a source electrode
11
which is electrically connected to the base region
6
and the source region
7
by Ohmic contact.
Meanwhile, in the above-described manufacturing method, as a first typical condition for determining the U-shaped groove, if a manufacturing condition in which film thickness of the silicon oxide film
12
=100 Å, film thickness of the silicon nitride film
11
=1500 Å and depth of the groove
14
=1.5 &mgr;m in the first step is selected, and formation second step is selected, although the groove shoulder
3
a
shown in
FIG. 1
is formed with an angle but radius of curvature R becomes small as 0.1 &mgr;m or less, dislocation is when the LOCOS oxide film
15
is formed, and leakage current is prone to be generated under reverse tolerance voltage between the drain region
5
and the base region
6
. Further, the gate oxide film
8
is prone to be destroyed due to concentration of electric field of the gate apply voltage at the groove shoulder
3
a
, and gate short circuit is prone to be generated.
Further, as a second typical condition, if a manufacturing condition in which film thickness of the silicon oxide film
12
=100 Å, film thickness of the silicon nitride film
13
=500 Å and depth of the groove
14
=1.5 &mgr;m in the first step is selected, and formation temperature of the LOCOS oxide film
15
=1100° C. in the second step is selected, the radius of curvature R of the groove shoulder
3
a
shown in
FIG. 1
becomes large as about 1 &mgr;m and current leakage under tolerance voltage or gate short circuit due to small radius of curvature R are not prone to be generated, but since the thickness of the silicon nitride film
13
is thin, abnormality in shape of the groove
3
is generated due to such inconvenience during the process that the silicon nitride film
13
is damaged or oxygen passes through the silicon nitride film
13
and for these reasons, leakage defect and short circuit defect are prone to be generated. If the radius of curvature R of the shoulder
3
a
is too large, the length of a channel formed in a direction of a surface of the semiconductor body becomes long, which is disadvantageous to on-resistance.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a field-effect transistor in which on-resistance is lowered by optimizing a condition for determining a shape of a U-shaped groove and a crystal plane of a side wall surface of the groove, and leakage defect and short circuit defect in the manufacturing process and product are suppressed, to a low level, from being generated and a manufacturing method thereof.
An insulated-gate type semicondu

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