Method of manufacturing an insulated gate field effect transisto

Details Method of manufacturing an insulated gate field effect transisto Method of manufacturing an insulated gate field effect transisto

1996-07-30

1998-10-20

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438287, 438692, H01L 218242

Patent

active

058245804

ABSTRACT:
A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. A gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After Chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon. The recesses are filled by a second layer of polysilicon that is Chem-Mech polished with the same slurry to remove polysilicon from the wafer surface. The polished polysilicon may be Reactive Ion etched until it is essentially coplanar with the wafer surface. The resulting FET has thicker gate oxide along its sides than in the center of its channel.

REFERENCES:
patent: 4356211 (1982-10-01), Riseman
patent: 4420874 (1983-12-01), Funatsu
patent: 4623437 (1986-11-01), Visca et al.
patent: 4797373 (1989-01-01), Malhi et al.
patent: 4986878 (1991-01-01), Malazgirt et al.
patent: 5075248 (1991-12-01), Yoon et al.
patent: 5078801 (1992-01-01), Malik
patent: 5217919 (1993-06-01), Gaul et al.
patent: 5240875 (1993-08-01), Tsou
patent: 5292679 (1994-03-01), Anzai
patent: 5313419 (1994-05-01), Chang
patent: 5316965 (1994-05-01), Philipossian et al.
patent: 5358894 (1994-10-01), Fazan et al.
patent: 5391511 (1995-02-01), Doan et al.
patent: 5397725 (1995-03-01), Wolstenholm et al.
patent: 5422294 (1995-06-01), Noble, Jr.
patent: 5448090 (1995-09-01), Geissler et al.
patent: 5482869 (1996-01-01), Kohyama
patent: 5489544 (1996-02-01), Rajeevakumar
patent: 5536675 (1996-07-01), Bohr

Affiliated with

Also associated with

Rating

Method of manufacturing an insulated gate field effect transisto does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing an insulated gate field effect transisto, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing an insulated gate field effect transisto will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-243795