Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-10-08
2004-08-17
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S052000, C438S619000, C438S381000
Reexamination Certificate
active
06777284
ABSTRACT:
The invention relates to a method of manufacturing an electronic device provided with metal regions that are mutually separated by air spaces, which method comprises the steps of
fining a first isolating layer on a substrate surface;
depositing a metal seed layer so that it covers the first isolating layer and exposed areas of the substrate surface; and
forming at least one metal region upon the exposed seed layer.
Such a method is known form U.S. Pat. No. 6,037,248. In this method there is preferably provided a plurality of isolating layers and metal regions, wherein the isolating layers are photoresist layers. Each forming of a metal region is followed by a polishing step, so as to remove the superfluous metal and the metal seed layer. Finally, the isolating layers are removed simultaneously.
It is a disadvantage of the known method that it is elaborate and uses a high number of metal deposition and processing steps to arrive at a final structure.
It is therefore a first object of the invention to provide a method of the kind mentioned in the opening paragraph, with a reduced number of processing steps to arrive at a final structure.
This object is realized in that
a second patterned isolating layer is formed on the seed layer according to a second pattern, a perpendicular projection of which on the substrate surface has an overlap with the first isolating layer;
the metal regions are formed such that they fill the patterns defined by the first and the second isolating layers, and
the second isolating layer and the seed layer are removed after forming of the metal regions, therewith obtaining the air spaces, the seed layer being removed in so far as it is not covered by the metal regions.
In the method of the invention a metal region is only formed after the provision of a first and a second isolating layer. Thereafter, or after providing further isolating layers and further level metal regions, the isolating layers are removed. In this removal the metal seed layer acts as etch stop layer. Hence, the number of metallisation steps and the number of polishing steps are cut to at least the half.
Although the number of removal steps increases, this is not dramatic, since etching is a well-controlled, clean and quick process step, especially compared to polishing. Besides, the method of the invention has the advantage that some of the isolating layers can be maintained if so desired. This allows the formation of functional entities within the structure of metal regions that are mutually separated with air spaces.
In a first embodiment the first isolating layer is removed after removal of the seed layer. In this embodiment a structure equal to the known structure is obtained. This embodiment is in particular advantageous if the pattern formed in the first isolation layer includes contact holes or vias extending to the substrate surface. The capacitive coupling between the vias that have to transmit signals individually, is then reduced.
In a second embodiment the first isolating layer is not removed, but maintained. In a preferred case a metallisation layer is present under the first isolating layer. This allows the definition of elements such as thin-film capacitors in the structure. It is therefore advantageous that the first isolating layer has a high dielectric constant, for example a relative dielectric constant of 7.0 or more. Materials that have such a dielectric constant are for instance Si
3
N
4
, Ta
2
O
5
, BaZrTiO
3
. Other materials are known to the person skilled in the art. Other elements are for instance two-layer inductors. Therewith it is advantageous that the first isolating layer contains a material with a high magnetic susceptibility, such as ferrites, composites with ferrite particles, and the like.
In a further embodiment the method comprises before removal of the second isolating layer the steps of:
forming a third patterned isolating layer on the metal regions;
depositing an additional metal seed layer so that it covers the third patterned isolating layer and exposed areas of the metal regions;
forming a fourth patterned isolating layer on the additional seed layer according to a fourth pattern;
forming second level metal regions upon the exposed seed layer, so as to fill the pattern defined by the third and the fourth isolating layers; and
removing the fourth isolating layer, the additional metal seed layer, in so far as the seed layer is not covered by the formed second level metal regions, and the third isolating layer.
In this embodiment a multilevel structure is provided. Such a multilevel structure can be used as an interconnect structure for an integrated circuit.
It is advantageous if in the multilevel structure a micro-electromechanical element is defined. Therein the element comprises:
a first electrode in the metallisation layer;
a second electrode in a second level metal region, which second electrode faces the first electrode and is substantially free-standing, such that it is movable towards the first electrode; and
at least one via extending from the second level metal regions to the metal regions, the via providing an electrical connection and mechanical support, a perpendicular projection of the metal region on the metallisation layer substantially non-overlapping with the first electrode.
Micro-electromechanical elements are known per se, for example from WO-A 01/61848. They are proposed for instance as switches and tunable capacitors for applications in the RF domain. With this embodiment, such elements may be manufactured as discrete elements, be provided in passive networks, or inside an interconnect structure of an integrated circuit. Therewith the seed layer can be used as an etch stop layer, that protects the underlying first isolating layer. Preferably the first isolating layer is not removed, but maintained so as to act as dielectric layer. The element is in that case a tunable capacitor of which the tuning range is enhanced considerably, in comparison with an embodiment without dielectric layer. Alternatively, The first isolating layer may be chosen so as to act as a protecting and/or anti-sticking layer. It could then even contain conductive particles. This is suitable if the element is to be used as a switch.
In the embodiment of the multilevel structure, it is preferred that the second and third isolating layers are removed in a single step. It is therefore preferred that these isolating layers contain the same material, which is a photoresist by preference. The seed layers are removed in another removal step. The removal preferably takes place by means of etching. If the seed layers contain the same material as the metal regions, such as copper, or if the etchant for the seed layers also etches the metal regions, it is preferred that the definition of the patterns is modified thereto, i.e. the patterns are designed larger so as to allow a size reduction during the removal steps.
The multilevel structure formed may be present on a planarized substrate. Alternatively, the substrate may contain cavities, wherein the multilevel structure is provided. Such structure can be used to provide a cap on top of the structure. Also the sidewalls of such a structure may provide additional mechanical strength. Further on, spacers and a capping layer may be present on the substrate to provide a cover for the multilevel structure. The capping layer may be provided on top of the metal regions before the removal of the isolating layers and the one or more seed layers. In that case it must be etch resistant against the etchants used. A suitable combination is for instance a ceramic or silicon oxide capping layer, with polymeric photoresists and copper metal layers.
REFERENCES:
patent: 6355551 (2002-03-01), Reinberg
Rijks Theodoor Gertrudis Silvester Maria
Van Melick Nicolaas Gerardus Henricus
Koninklijke Philips Electronics , N.V.
Tsai H. Jey
Zawilski Peter
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