Method of manufacturing a trench gate field effect...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S138000, C438S970000

Reexamination Certificate

active

06331467

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a method of manufacturing a semiconductor device comprising a trench gate field effect device. The device may be, for example, an insulated gate field effect power transistor or an insulated gate bipolar transistor. The invention also relates to a semiconductor device manufactured by such a method.
U.S. Pat. No. 5,378,655 (our reference: PHB33836) describes a method of manufacturing a semiconductor device comprising a trench gate field effect device wherein a semiconductor body having first and second major surfaces is provided having a first region of one conductivity type and a second region of the opposite conductivity type separating the first region from the first major surface. A trench is etched through the second semiconductor region and then a gate is provided within the trench with, in the example described in U.S. Pat. No. 5,378,655, the gate being an insulated gate having a gate dielectric region separating a conductive gate region from the trench walls. A source region of the one conductivity type separated from the first region by the second region is formed adjacent the trench so that a conduction channel area of the second region adjacent the trench provides a conduction path between the source and first regions which is controllable by the gate. Typically, the trench will define a regular array of parallel source cells each bounded by the trench.
As shown in the drawings of U.S. Pat. No. 5,378,655, the trench extends beyond the second region into the first region. Where such a device is operated in a reverse bias or blocking mode, large electrical fields can build up at the relatively sharp corners of the trench leading to breakdown at these points. It has previously been proposed, as shown in, for example, U.S. Pat. No. 5,387,528 (our reference: PHB33804), to provide each source cell with a central relatively highly doped deep region of the opposite conductivity type so as to move the avalanche breakdown point away from the trench corners into the centre of the source cell so as to enable the onset of avalanche breakdown to be delayed until higher voltages and to enable breakdown, if it does occur, to happen in a more controlled and reproducible manner. However, the introduction of such relatively highly doped central regions places a constraint on the minimum dimensions of the source cells which in turn places a constraint on the minimum on-resistance of the device because, for a given semiconductor surface area, the on-resistance is related to the channel width which itself is related to the size of the source cells.
SUMMARY OF THE INVENTION
It is an aim of the present invention to provide a method of manufacturing a semiconductor device comprising a trench gate field effect device which enables improved control over the properties of the device.
According to the present invention, there is provided a method of manufacturing a semiconductor device in which the etch stop layer is provided in the vicinity of the pn junction. Such a method is set out in claim
1
.
A method embodying the present invention enables the depth of the trench to be well-controlled. This enables the location of the bottom of the trench to be selected so as to optimise particular device characteristics.
In an embodiment, the etch stop layer is provided at the pn junction between the first and second regions so that the trench has the same depth as the second or body region of the device enabling the electric fields at the corners of the trench to be reduced and so reducing the possibility of breakdown at the trench corners or at least raising the reverse biassing voltage at which breakdown may occur at those trench corners.
This enables the build up of large electrical fields at the corners of the trench to be alleviated without the need for a relatively highly doped central region of the opposite conductivity type which would otherwise place constraints on the minimum size of the source cells. This therefore enables the source cells to be smaller than would be the case if the central regions were required and thus enables a lower specific ON-resistance.
In an embodiment, the etch stop layer is provided within the first region so that, after the trench has been formed, the trench extends deeper into the semiconductor body than the second region to enable a minimum specific ON-resistance to be achieved.
Thus by controlling the position of the etch stop layer, the depth of the trench can be well-controlled and the device breakdown characteristics optimised by placing the etch stop layer at the pn junction between the first and second regions or the minimum ON-resistance of the device optimised by controllably locating the etch stop layer within the first region. In either case, the thicknesses of the first and second regions, especially the first region, can be optimised so reducing series resistance and the ON-resistance of the device.
In an embodiment, a first portion of the trench is etched using an etching process selected to enable good control over the lateral dimensions of the trench while the final portion of the trench is etched using an etching process that enables the etching to be stopped at the etch stop layer. Preferably, the etching process used for the first portion of the trench is an anisotropic etching process such as a plasma etching process. In a preferred embodiment, the etching process used to etch the final portion of the trench is an isotropic etching process which etches the first and second regions selectively relative to the further region, that is the selective isotropic etchant etches the first and second regions considerably more quickly than the etch stop layer. The use of an isotropic etchant to etch the final part of the trench also has the advantage that the bottom corners of the trench will be rounded by the isotropic etching process so enabling the device to have a higher breakdown voltage and a more uniform oxide thickness than would be the case if an anisotropic etching process had been used to etch the entirety of the trench. In a preferred embodiment, 90% of the depth of the trench is etched using an anisotropic etching process and the final 10% of the depth of the trench is etched using a selective isotropic etching process thereby enabling good control over the lateral extent of the trench whilst still allowing for rounding of the corners of the trench to alleviate the high fields at the corners. Greater rounding of the corners of the trench could be achieved by increasing the proportion of the depth etched by the isotropic etching process but this would give less control over the lateral extent of the trench.
In an embodiment the first and second regions are provided as regions of monocrystalline silicon and the etch stop layer is provided as a silicon-germanium (SiGe) layer. The product of the thickness of the etch stop layer and the relative difference in lattice constants of silicon and germanium should be such that mechanical stress or strain due to the difference in the lattice constants does not lead to the creation of fatal dislocation. In a preferred embodiment, the silicon and germanium layer has 10 atom % germanium and a thickness of 40 nanometers.
In a preferred embodiment where the first and second regions are monocrystalline silicon regions and the etch stop layer is a silicon-germanium region a solution of potassium hydroxide (KOH) is used to etch the first and second regions selectively with respect to the etch stop layer.
Generally, where the etch stop layer is intended to be at the pn junction between the first and second regions, then the etch stop layer will initially be formed between the first and second regions.
However, the position of the further or etch stop region may be adjusted so as to compensate for repositioning of the pn junction between the first and second regions due to diffusion during subsequent manufacturing steps which are carried out at a relatively high temperature.
Preferably, the first, second and further regions are formed as epitaxial layers in a

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