Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-11-02
2004-04-27
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S163000, C438S166000, C438S487000
Reexamination Certificate
active
06727124
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electro-optical device (semiconductor device) including a circuit that is composed of a thin film transistor (hereinafter referred to as TFT) formed on an insulator, and to a method of manufacturing the same. Specifically, the present invention relates to an electro-optical device (semiconductor device) represented by a liquid crystal display device in which a pixel portion and a driving circuit provided in the periphery of the pixel portion are formed on the same substrate, and to an electronic appliance using the electro-optical device (semiconductor device) as a display unit.
2. Description of the Related Art
In recent years, a large number of TFTs have been developed which use as an active layer a polycrystalline semiconductor film obtained by crystallizing an amorphous semiconductor film that is formed on an insulating substrate such as a glass substrate. In particular, polysilicon films or other crystalline silicon films obtained by crystallizing an amorphous silicon film are often employed.
A process of forming a large-area polysilicon film on a substrate that has a low resistivity against heat, such as a glass substrate and a plastic substrate, is also a research and development theme that continues to attract researchers. Crystallization using laser light and crystallization involving doping with a crystallization-promoting catalytic element and heat treatment are given as examples of a so-called low temperature crystallization technique.
One of the latter crystallization techniques, in which an amorphous silicon film is doped with a catalytic element for promoting crystallization and then subjected to heat treatment to be crystallized, is disclosed in Japanese Patent Application Laid-open No. Hei 7-130652.
According to this technique, the temperature required to crystallize an amorphous silicon film can be lowered by 50 to 100° C. and time required for crystallization is shortened to ⅕ to {fraction (1/10)} as well with the effect of a catalytic element. The technique thus makes it possible to form a crystalline silicon film having a large surface area on a substrate of low heat resistance as those mentioned above. Also, it is a confirmed fact that a crystalline silicon film obtained by this technique has an excellent crystallinity.
The above crystallization technique using a catalytic element employs a metal element such as Ni and Co for the catalytic element. These metal elements generate a great energy level in the silicon film to trap carriers and cause recombination of the carriers. Therefore, when the obtained crystalline silicon film is used to form a TFT, it is expected that the electric characteristic and the reliability of the TFT are affected.
In addition, the catalytic element remaining in the silicon film has been observed to segregate irregularly. The catalytic element segregates most in crystal grain boundaries, and it is considered that this segregation provides a leak path for a small amount of current and causes an abrupt increase in OFF current (a current flowing in a TFT when the TFT is in an OFF state).
For that reason, the catalytic element has to be quickly removed, or reduced to a degree that it does not exert any electric influence, once the crystallization step is finished. A technique that utilizes the gettering effect can be used to remove or reduce the catalytic element.
One of existing gettering methods includes the steps of partially covering, with a resist mask, a crystalline silicon film obtained by crystallizing an amorphous silicon film with the help of a metal element so as to cover a portion of the crystalline silicon film that is to serve as a channel forming region in a semiconductor layer of a TFT, and doping the rest of the semiconductor layer of the TFT with P or other Group
15
elements effective in gettering in high concentration to form a region that promotes gettering (the region is hereinafter called a gettering sink). Another example of the existing gettering methods involves similarly covering the region of the crystalline silicon film that serves as the channel forming region of the TFT with a resist mask and forming a gettering sink containing P or other Group
15
elements in high concentration in the periphery of a portion of the crystalline silicon film that forms the semiconductor layer of the TFT. However, these methods need the mask formation step, thereby resulting in increases in the number of masks and the number of manufacturing steps. Therefore, the methods have problems in productivity, yield, and manufacturing cost.
Further, when a p-channel TFT is formed, a region for forming the p-channel TFT is doped with a p-type impurity element (boron (B), in this example) to form a source region and a drain region after doped with a large amount of phosphorus for gettering. In order to invert the n-type conductivity of the region for forming the p-channel TFT, which has been given by phosphorus (P) through the previous doping, the region has to be doped with boron (B) in considerably high concentration.
This brings a problem of reduced throughput in the doping step, or a problem of difficulty in improving the crystallinity of the source region and the drain region by heat treatment.
The semiconductor layer has to be doped with phosphorus (P) in order to carry out the gettering treatment. However, doping with a p-type impurity element (typically, boron (B)) is also needed to form a p-channel TFT. Since the step of doping with an n-type impurity element (phosphorus (P)) precedes the step of doping the semiconductor layer of the p-channel TFT with boron (B), the layer has to be doped with the p-type impurity element in a concentration high enough to invert the n-type conductivity to the p-type conductivity (called counter doping or cross doping). The concentration of boron (B) in the layer has to be higher than the concentration of phosphorus (P) with which the layer has previously been doped. However, if the concentration of the impurity element is too high, the resistivity of the source drain region is raised to lower ON current. Counter doping is also unsatisfactory in terms of manufacture cost and productivity because it requires excessive ions as acceptors for doping.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above, and an object of the present invention is therefore to provide a highly reliable electro-optical device and a method of manufacturing the electro-optical device by efficiently gettering a catalytic element used to promote crystallization of an amorphous silicon film.
One of the features of the presnet invention is an electric device comprising a semiconductor layer on an insulator, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film, wherein the electric device has an n-channel TFT and a p-channel TFT, wherein the semiconductor layer in the p-channel TFT includes a channel forming region (
13
), a region (
11
) containing an n-type impurity element and a p-type impurity element, and a region (
12
) containing only a p-type impurity element, and wherein a wiring line for electrically connecting the TFTs to one another is connected to the region (
12
) containing only a p-type impurity element in the p-channel TFT.
Another one of the features of the presnet invention is an electric device comprising a semiconductor layer on an insulator, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film, wherein the electric device has an n-channel TFT and a p-channel TFT, wherein the semiconductor layer in the p-channel TFT includes a channel forming region (
13
), a region (
21
a,
21
b
) containing an n-type impurity element and a p-type impurity element, and a region (
22
) containing only a p-type impurity element, wherein the region (
22
) containing only a p-type impurity element is sandwiched between the region (
21
a
) containing an n-type impurity element and a p-type impurity elemen
Makita Naoki
Matsuo Takuya
Nakajima Setsuo
Ohnuma Hideto
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Jr. Carl Whitehead
Semiconductor Energy Laboratory Co,. Ltd.
Smoot Stephen W.
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