Method of manufacturing a semiconductor memory device with a hig

Details Method of manufacturing a semiconductor memory device with a hig Method of manufacturing a semiconductor memory device with a hig

1997-07-25

1999-11-09

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438 3, H01L 218242

Patent

active

059813318

ABSTRACT:
In a semiconductor memory device and a manufacturing method thereof, a barrier metal layer having a step h.sub.2 which is smaller than the step h.sub.1 at the upper end of a contact hole is formed on the surface opposite to the contact hole. The barrier metal layer has a nitrogen concentration gradient which becomes higher from its lower layer to its upper layer. A semiconductor memory device provided with a highly planer capacitor lower electrode, and a method of manufacturing the semiconductor memory device can thus be provided.

REFERENCES:
patent: 5448512 (1995-09-01), Hachisuka et al.
patent: 5506166 (1996-04-01), Sandhu et al.
patent: 5567964 (1996-10-01), Kashihara et al.
patent: 5699291 (1997-12-01), Tsunemine

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