Method of manufacturing a semiconductor memory device which...

Details Method of manufacturing a semiconductor memory device which... Method of manufacturing a semiconductor memory device which...

2001-09-28

2004-01-13

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06677203

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a method for fabricating the device, and more particularly relates to a nonvolatile semiconductor memory device of which the floating gate electrode is formed on a side face of the control gate electrode thereof and a method for fabricating the device.
Flash EEPROM (Electrically Erasable Programmable ROM) devices are well known as electrically erasable and programmable nonvolatile memory devices.
Recently, U.S. Pat. No. 5,780,341 disclosed a memory cell structure for a flash EEPROM semiconductor memory device, which includes: a step region formed in the drain region thereof; a floating gate electrode formed so as to overlap with the step region; and a control gate electrode adjacent to the floating gate electrode. In this memory cell, channel hot electrons are created by applying a voltage to the drain region and the control gate electrode. Then, a write operation is carried out by injecting the created hot electrons into the floating gate electrode located over the step region, i.e., in the direction in which the electrons move.
Hereinafter, the known semiconductor memory device including the step region in its drain region will be described with reference to the accompanying drawings.
FIGS. 10A
,
10
B and
10
C illustrate a structure for the known semiconductor memory device.
FIG. 10A
illustrates a planar layout of the device.
FIG. 10B
illustrates a cross-sectional structure for part of the device including an active region.
FIG. 10C
illustrates a cross-sectional structure for part of the device including an isolation film.
As shown in
FIGS. 10A
,
10
B and
10
C, multiple control gate electrodes
104
are formed over a semiconductor substrate
101
made of silicon with a gate insulating film
103
interposed between the electrodes
104
and the substrate
101
. Multiple shallow trench isolations (STIs)
102
are also formed on the substrate
101
so as to be spaced apart from each other in the direction in which the control gate electrodes
104
extend, i.e., in the width direction of the control gate electrodes
104
. Each of the STIs
102
crosses with associated ones of the control gate electrodes
104
.
On a side face of each of the control gate electrodes
104
, a floating gate electrode
106
is formed with an insulating film
105
, which will be a capacitance insulating film and a tunnel insulating film, interposed between the floating gate electrode
106
and the control gate electrode
104
. The floating gate electrode
106
is located in an active region between adjacent ones of the STIs
102
on the semiconductor substrate
101
.
As shown in
FIG. 10B
, a step region
101
a
exists in part of the active region under each floating gate electrode
106
. Also, a drain region
107
has been defined in another part of the active region closer to the floating gate electrode
106
and a source region
108
has been defined in still another part of the active region opposite to the floating gate electrode
106
.
As shown in
FIGS. 10B and 10
c,
the drain region
107
extends continuously in the gate width direction of the control gate electrode
104
. In this manner, in the known semiconductor memory device, the drain region
107
is shared between multiple cells and thus a drain line can be formed on the semiconductor substrate
101
. Accordingly, it is not necessary to form an additional drain line over the semiconductor substrate
101
with contacts interposed between the drain line and the substrate. Thus, the number of contacts needed can be reduced. As a result, the proportion of the contacts to the total cell area can be reduced, thus contributing to the downsizing of the device.
Hereinafter, a method for fabricating the known semiconductor memory device will be described with reference to the accompanying drawings.
FIGS. 11A through 17C
illustrate respective process steps for fabricating the known semiconductor memory device. In each of these drawings, A illustrates a planar layout of the structure, B illustrates a cross-sectional structure including an active region and C illustrates a cross-sectional structure including STIs.
First, as shown in
FIGS. 11A
,
11
B and
11
C, multiple slip-shaped STIs
202
are formed on a semiconductor substrate
201
of silicon so as to be spaced apart from each other.
Next, as shown in
FIGS. 12A
,
12
B and
12
C, the exposed surface of the semiconductor substrate
201
is thermally oxidized, thereby forming a first silicon dioxide film on the semiconductor substrate
201
. Then, a first polysilicon film and a first insulating film
205
are deposited in this order on the first silicon dioxide film by a CVD process. Then, a mask pattern
206
for forming control gate electrodes is defined by a photolithographic process, and the first insulating film
205
, the first polysilicon film and the first silicon dioxide film are dry-etched using the mask pattern
206
. In this manner, control gate electrodes
204
are formed out of the first polysilicon film and control gate insulating films
203
are formed out of the first silicon dioxide film.
Next, as shown in
FIGS. 13A
,
13
B and
13
C, after the mask pattern
206
has been removed, a second insulating film is deposited over the semiconductor substrate
201
by a CVD process. Then, the second insulating film is dry-etched, thereby forming sidewall insulating films
207
out of the second insulating film on the side faces of the control gate electrodes
204
.
Next, as shown in
FIGS. 14A
,
14
B and
14
C, a mask pattern
208
, which has an opening over part of the active region of the semiconductor substrate
201
where the drain region will be defined, is defined over the substrate
201
for purpose of forming the step regions by a photolithographic process. Then, the step regions
201
a
are defined in the drain forming region of the semiconductor substrate
201
by a dry etching process using the mask pattern
208
, first insulating films
205
and sidewall insulating films
207
as a mask.
Then, as shown in
FIGS. 15A
,
15
B and
15
C, after the mask pattern
208
has been removed, the sidewall insulating films
207
are removed by a wet etching process. Subsequently, the side faces of the control gate electrodes
204
and the step regions
201
a
are thermally oxidized, thereby forming a second silicon dioxide film
209
which will be a capacitance insulating film and a tunnel insulating film. Then, a second polysilicon film
210
A is deposited on the second silicon dioxide film
209
by a CVD process. Thereafter, a mask pattern
211
, which has an opening over the drain forming region to extend in the gate width direction of the control gate electrodes
204
, is defined on the second polysilicon film
210
A by a photolithographic process. Then, the second polysilicon film
210
A is dry-etched using the mask pattern
211
and the first insulating films
205
as a mask, thereby forming sidewall-shaped polysilicon films
210
B out of the second polysilicon film
210
A.
Subsequently, as shown in
FIGS. 16A
,
16
B and
16
C, after the mask pattern
211
has been removed, a mask pattern
212
is defined by a photolithographic process to mask the drain forming regions of the semiconductor substrate
201
and sidewall-shaped polysilicon films
210
B. Then, the second poly-silicon film
210
A and the sidewall-shaped polysilicon films
210
B are dry-etched using the mask pattern
212
and the first insulating films
205
as a mask, thereby forming island-shaped floating gate electrodes
210
C, overlapping the step regions
201
a,
out of the sidewall-shaped polysilicon films
210
B in the drain forming regions.
Next, as shown in
FIGS. 17A
,
17
B and
17
C, after the mask pattern
212
has been removed, arsenic ions are implanted using the first insulating films
205
and the floating gate electrodes
210
C as a mask. In this manner, drain regions
214
are defined in the drain forming regions and source regions
215
are defined in the source forming regions.
The known fab

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