Method of manufacturing a semiconductor memory device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438248, H01L 218242

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active

060157313

ABSTRACT:
The first element separation oxide film consisting of a plurality of line-shaped portions parallel to the bit line is formed on the surface of the P-type silicon substrate. The first and second trenches are formed in that portion of the P-type silicon substrate which is located between an adjacent pair of line-shaped portions of the first element separation oxide film such that both sides of the trenches come in contact with the first element separation oxide film. A sheath plate capacitor is formed in each of the trenches. The second element separation oxide film having a thickness less than that of the first element separation oxide film is formed on that portion of the surface of the P-type silicon substrate which is located between the first and second trenches.

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Toru Kaga et al., IEEE Transactions on Electron Devices, dated Aug. 8, 1988, vol. 35, No. 8, "Half-V.sub.cc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate Wiring" pp. 1257-1263.

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