Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-12-25
2007-12-25
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S399000, C438S597000, C438S639000
Reexamination Certificate
active
11155174
ABSTRACT:
Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.
REFERENCES:
patent: 6458692 (2002-10-01), Kim
patent: 6924229 (2005-08-01), Cheong et al.
patent: 7153727 (2006-12-01), Lee et al.
patent: 2004/0099957 (2004-05-01), Jin
patent: 2004/0140486 (2004-07-01), Lee et al.
Ahn Tae-hyuk
Jeon Jeong-sic
Seo Jung-woo
Chen Jack
Marger & Johnson & McCollom, P.C.
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