Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-06-24
2004-04-06
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S263000, C438S266000
Reexamination Certificate
active
06716701
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device capable of stably keeping the threshold voltage of the flash memory device.
2. Background of the Related Art
In general, a flash memory device comprises a memory cell array for storing data and a peripheral circuit for storing/reading data at/from the memory cell array. Each of the memory cells formed in the memory cell region includes a gate of a structure on which a tunnel oxide film, a floating gate, a dielectric film and a control gate are stacked, and the source and the drain formed at both sides of the gate. The memory cell is programmed as hot electrons are injected into the floating gate. Also, the memory cell is erased as the injected electrons are discharged.
The data retention ability of the flash memory cell constructed above, is decided by the dielectric constant of the dielectric film formed between the floating gate and the control gate. Accordingly, in order to obtain a high dielectric constant, a deposition process is implemented at high temperature so that the dielectric film of a high density is formed. If the process is performed at high temperature as above, however, many problems relating to characteristics of the device occur. In particular, as the threshold voltage of the transistor is changed, it adversely affects the reliability of the device.
A common CMOS device using a P type substrate has wells into which different dopants are injected. A P type dopant is injected into the channel regions of the NMOS and PMOS transistors, which are formed in their respective wells, in order to control the threshold voltage. In case of the PMOS transistor, however, it is experienced by several high-temperature annealing processes in its manufacture process. Therefore, the depletion layer is increased at a buried channel due to transient enhanced diffusion (TED) of the dopant injected into the source and the drain, which makes low the threshold voltage. Such reduction in the threshold voltage occurs over the entire wafer regions. Accordingly, there is a difficulty that the depth of the junction must be further shallow in order to stabilize the threshold voltage.
Conventionally, a trench of a shallow size is formed in the substrate using the pad oxide film and the pad nitride film as a mask. An isolation film is then formed within the trench. After wells are formed in order to form a CMOS device, a P type ion for threshold voltage control is injected in order to control the threshold voltage of the transistor that will be formed in every region. At this time, in case of the NMOS transistor, B11 ion is injected. In case of a PMOS transistor having the buried channel, BF
2
ion is injected in order to make the depth of the channel shallow. Thereafter, a tunnel oxide film and a polysilicon layer are formed over the semiconductor substrate in the memory cell region and the peripheral circuit region. Next, a dielectric film having an ONO (oxide
itride/oxide) structure is formed by means of a low-pressure chemical vapor deposition (LPCVD) method. After a mask is formed in the memory cell region, the dielectric film, the polysilicon layer and the tunnel oxide film, in the exposed peripheral circuit region, are removed. In order to form gates of a high-voltage transistor and a low-voltage transistor over the semiconductor substrate in the peripheral circuit region, a gate oxide film and a polysilicon layer are formed. Subsequent processes are same to common manufacture processes of the flash memory devices.
If the mentioned conventional manufacture method is utilized, the P type dopant injected in order to control the threshold voltage is experienced by TED in a subsequent annealing process. Therefore, the concentration of the ion in the channel region is reduced and the threshold voltage is changed accordingly.
FIG. 1A
shows the result of measuring the threshold voltage in the SRAM for which annealing steps at high temperature is little.
FIG. 1B
shows the result of measuring the threshold voltage in the flash memory device for which annealing steps at high temperature is many. In case of the SRAM, it could be seen that change in the threshold voltage is small both in case that the pattern is big (line A) and in case of a real size (line B). However, in case of the flash memory devices, it can be seen that variation in the threshold voltage is large. Further, in case of the flash memory devices, it could be seen that the threshold voltage over the entire wafer regions is irregularly distributed, as shown in
FIG. 2
Such variation and irregular distribution in the threshold voltage greatly affects the reliability of the device. In particular, it makes difficult implementing a transistor having a stable electrical characteristic.
SUMMARY OF THE INVENTION
Accordingly, the present invention is contrived to substantially obviate one or more problems due to limitations and disadvantages of the related art, and an object of the present invention is to provide a method of manufacturing semiconductor memory devices, by which an ion implantation layer is formed in a given depth of a semiconductor substrate, thereby preventing transit enhanced diffusion of a dopant that was gettered on the semiconductor substrate upon implantation of the ion into the well.
In a preferred embodiment, the method of manufacturing the semiconductor memory devices according to the present invention is characterized in that it comprises the steps of forming a trench in an isolation region of a semiconductor substrate and then forming an isolation film within the trench, forming a screen oxide film on the semiconductor substrate and then forming a triple well through an ion implantation process using a given mask, removing the screen oxide film, forming a tunnel oxide film and a first polysilicon layer on the entire structure and then patterning the first polysilicon layer to form a floating gate over the semiconductor substrate in the memory cell region, forming a dielectric film and a second polysilicon layer on the entire structure and then patterning the second polysilicon layer to form a control gate over the semiconductor substrate in the memory cell region, injecting an ion for controlling the threshold voltage into the exposed semiconductor substrate of the peripheral circuit region, and forming a gate oxide film and a third polysilicon layer over the semiconductor substrate of the peripheral circuit region, thus forming a gate of a transistor.
The method further comprises the step of after the step of forming the triple well, injecting an inert ion into a given depth of the semiconductor substrate and then implementing a rapid thermal process to form an ion implantation layer. The inert ion is nitrogen (N
2
) and is injected with energy of 30~100 KeV at the dose of 1E13~5E14 ion/cm
2
. The rapid thermal process is implemented under nitrogen (N
2
) atmosphere at a temperature of 900~1100° C. for 5~30 seconds.
The ion for controlling the threshold voltage is BF
2
and is injected with energy of 10~50 KeV at the dose of 1E11~1E14 ion/cm
2
.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In another aspect of the present invention, it is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6258668 (2001-07-01), Lee et al.
Kwak Noh Yeal
Yang Hong Seon
Jacobson & Holman PLLC
Tsai H. Jey
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