Method of manufacturing a semiconductor memory device...

Details Method of manufacturing a semiconductor memory device... Method of manufacturing a semiconductor memory device...

2000-12-26

2002-03-05

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S240000

Reexamination Certificate

active

06352898

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor memory device and, more particularly, to a method for manufacturing a capacitor for use in a ferroelectric random access memory (FeRAM) device with a high polarization value and improved short failure and leakage current characteristics.
DESCRIPTION OF THE PRIOR ART
With the recent progress of film deposition techniques, applications for a nonvolatile memory cell using a ferroelectric thin film have increasingly been developed. This nonvolatile memory cell is a high-speed rewritable nonvolatile memory cell utilizing the high-speed polarization/inversion and the residual polarization of the ferroelectric capacitor thin film.
Therefore, in a ferroelectric random access memory (FeRAM), a capacitor thin film with ferroelectric properties such as strontium bismuth tantalate (SBT) and lead zirconate titanate (PZT) is increasingly used in place of a conventional silicon oxide film or a silicon nitride film, because it assures a low-voltage and high-speed performance, and further, does not require periodic refresh to prevent loss of information during standby intervals like a dynamic random access memory (DRAM).
Since a ferroelectric material has a dielectric constant having a value ranging from hundreds to thousands, and stabilized residual polarization property at room temperature, such material is being applied to the non-volatile memory device as the capacitor thin film. When employing the ferroelectric capacitor thin film in the non-volatile memory device, information data are stored by polarization of dipoles when an electric field is applied thereto. Even if the electric field is removed, the residual polarization still remains so that the information data, i.e., 0 or 1, can be stored.
Meanwhile, to employ a ferroelectric capacitor for use in the semiconductor memory device effectively, there are several conditions required. First, a short failure should not occur; second, the ferroelectric capacitor should have a high polarization value; and third, leakage current should be minimized. The short failure and the leakage current problems may occur mainly because the ferroelectric capacitor thin film of the capacitor structure has vacancies therein or does not have a uniform thickness. Thus, if the ferroelectric capacitor thin film has a portion which is relatively thinner than another portion thereof, a short failure and/or leakage current may occur around the thinner portion. Further, the larger the grain size of the ferroelectric capacitor thin film, the higher the polarization value of the capacitor thin film.
In manufacturing the ferroelectric capacitor, there are typically two annealing steps for enhancing reliability of the ferroelectric capacitor. One annealing step is carried out in order to form a phase of the ferroelectric capacitor thin film after depositing it on a bottom electrode. In more detail, this annealing step includes a rapid thermal annealing (RTA) for producing nuclei in the ferroelectric capacitor thin film and a thermal annealing step in a furnace for growing up the grains of the ferroelectric. The second annealing step is a post thermal treatment including a first thermal treatment for recovering the ferroelectric property that has been degraded during formation of the capacitor structure by a selective etching step, and a second thermal treatment for planarizing an interlayer insulating layer formed on the capacitor structure.
Generally, the ferroelectric capacitor thin film has a smooth surface after the RTA step. However, after the thermal annealing step in the furnace, i.e., after the grains are grown up to a predetermined size, the ferroelectric capacitor thin film has a rough surface incorporating therein vacancies.
According to prior art techniques for manufacturing the ferroelectric capacitor, thermal treatments are carried out by two kinds of methods. The first method includes the steps of carrying out the RTA step for producing the nuclei, annealing in the furnace, and forming the top electrode on the ferroelectric capacitor thin film. However, using this method the ferroelectric film does not have a uniform thickness, such that vacancies may exist in the ferroelectric. Therefore, while this method has an advantage of a high polarization value when forming the top electrode on the ferroelectric capacitor thin film, short failure and leakage current may occur due to the vacancies and the varying thickness of the ferroelectric.
The second method is performed by carrying out the RTA step, forming the top electrode on the ferroelectric capacitor thin film, and carrying out the recovery step and annealing step. While this second method has a good property against the short failure and the leakage current, it has a limited capacity to grow up the grains, thereby inducing a low polarization value. When using SBT or SBTN (Sr
x
Bi
y
(Ta
i
Nb
j
)
2
O
9
) as the ferroelectric material, it is preferable that the post-thermal treatment for inducing a grain growth should be carried out at approximately 700° C. for a long time. But, this high temperature thermal treatment may also create a problem by producing the vacancies and shrinkages in the top electrode of the ferroelectric capacitor.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for manufacturing a ferroelectric random access memory (FeRAM) device with enhanced polarization, and improved short failure and leakage current characteristics by employing supplementary thermal treatment.
In accordance with one aspect of the present invention, there is provided a method for use with a FeRAM device, the method comprising the steps of a) preparing an active matrix provided with a transistor, diffusion regions, an isolation region, a bit line, a first insulating layer and a second insulating layer; b) forming a first conductive layer and then a dielectric layer on the active matrix; c) carrying out a rapid thermal annealing (RTA) for producing nuclei in the dielectric layer; d) forming a second conductive layer on top of the dielectric layer; e) carrying out a thermal annealing in a furnace; f) forming a capacitor Structure provided with a top electrode, a capacitor thin film and a bottom electrode by patterning the second conductive, the dielectric and the first conductive layers into a first predetermined configuration; g) carrying out a first recovery; h) forming a third insulating layer on the capacitor structure and the second insulating layer; i) patterning the third insulating layer to form a first opening and a second opening; and j) carrying out a second recovery.


REFERENCES:
patent: 5374578 (1994-12-01), Patel et al.
patent: 2001/0013614 (2001-08-01), Joshi et al.

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