Method of manufacturing a semiconductor integrated circuit devic

Details Method of manufacturing a semiconductor integrated circuit devic Method of manufacturing a semiconductor integrated circuit devic

1996-11-25

1999-01-05

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438277, 438279, H01L 218244

Patent

active

058562168

ABSTRACT:
A semiconductor integrated circuit device includes a first conductor formed on a main surface of a semiconductor substrate with an insulating film therebetween, and a second conductor formed with an insulating film therebetween so as to be placed near one side of the first conductor and to have its one end extended over a top surface of the one side of the first conductor. The semiconductor integrated circuit device further includes an impurity diffusion layer at the main surface of the semiconductor substrate under a region where first and second conductors are close to each other. In accordance with this structure, higher degree of integration of a memory cell can be readily achieved by a relatively simple manufacturing process. Such a structure can be manufactured by forming the impurity diffusion layer at the surface of the semiconductor substrate, forming first conductor by patterning a first conductor layer, forming a second conductor layer, and forming a second conductor by patterning the second conductor layer.

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"A High Density SRAM Cell Using Poly-si PMOS FET," Yamanaka et al., ICD89-26, pp. 1-6. No date.
"A 7.5-NS 32K x 8 CMOS SRAM," Hiroaki Okuyama et al., IEEE Journal of Solid-State Circuits, vol. 23, No. a5, Oct. 1988, pp. 1054-1058.

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