Method of manufacturing a semiconductor integrated circuit...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S270000, C438S275000, C438S589000

Reexamination Certificate

active

10920247

ABSTRACT:
A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.

REFERENCES:
patent: 6130454 (2000-10-01), Gardner et al.
patent: 6177704 (2001-01-01), Suzuki et al.
patent: 6316807 (2001-11-01), Fujishima et al.
patent: 6781197 (2004-08-01), Fujishima et al.
patent: 2004/0032005 (2004-02-01), Williams et al.
patent: 2004/0063291 (2004-04-01), Williams et al.
patent: 04-306881 (1992-10-01), None
patent: 2002-141501 (2000-05-01), None
patent: 2000-323706 (2000-11-01), None
patent: 2002-280549 (2002-09-01), None
N. Fujishima et al., A High Density, Low On-resistance, Trench Lateral Power MOSFET with a Trench Bottom Source Contact, IEEE Transactions on Electron Devices, vol. 49, No. 8, Aug. 2002.
Akio Kitamura, et al., “Self-Isolated and High Performance Complementary Lateral DMOSFETs With Surrounding-Body Regions”, Proceedings of 1995 Intl. Symposium On Power Semiconductor Devices & ICs., Yokohama.
N. Fujishima, et al., “A High Density, Low On-resistance, Trench Lateral Power MOSFET with a Trench Bottom Source Contact”, Proceedings of 2001 Intl. Symposium on Power Semiconductor Devices & ICs., Osaka.
U.S. Appl. No. 10/272,304, filed Oct. 17, 2002, Naoto Fujishima et al., Fuji Electric Co., Ltd.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of manufacturing a semiconductor integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a semiconductor integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor integrated circuit... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3931914

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.