Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-06
2004-01-13
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S276000, C438S419000, C438S527000
Reexamination Certificate
active
06677194
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor integrated circuit device including a complementary metal insulator semiconductor transistor (CMIS), and in particular, to a method of manufacturing a semiconductor integrated circuit device in which doping steps for wells, channels, and gate electrodes are conducted using a reduced number of photomasks.
Heretofore, the ion implantation steps for wells and channels are conducted before deposition of materials for gate electrodes. Therefore, in the manufacturing of the CMIS, after photolithography is achieved to implant ions in the wells and the channels, photolithography for ion implantation of the gate electrodes must be conducted for each transistor areas respectively of the n-type and p-type channels.
Referring next to
FIGS. 33
to
47
, description will be given of a doping technique for wells, channels, and gate electrodes of the prior art according to examples of methods of manufacturing semiconductor integrated circuit devices respectively including n-type MIS (NMIS) and p-type MIS (PMIS) transistors each of which has two kinds of threshold voltages.
On one surface of a silicone substrate
101
, a field oxide film
102
to isolate transistors from each other is formed, for example, by trench isolation. On the oxide film
102
, an about 15 nanometer (nm) thick sacrificial oxide film
103
is formed. Using first photoresist as a mask
104
, boron ions are implanted with an impurity density of 5×10
12
/cm
2
onto first and second NMIS transistor forming areas (FIG.
33
). After removing the first photoresist
104
, phosphorus ion implantation is conducted with an impurity density of about 5×10
12
/cm
2
onto first and second PMIS transistor forming areas using second photoresist
105
as a mask (FIG.
34
). After removing the photoresist
105
, a predetermined activation step is conducted in nitrogen ambient at about 900° C. to respectively form p-type wells
106
and n-type wells
107
(FIG.
35
).
Using third photoresist
108
and the field oxide film
102
as a mask, boron ion implantation is conducted with an impurity density of about 1×10
13
/cm
2
onto punchthrough stopper forming areas of the first and second NMIS transistors (FIG.
36
). Using the third photoresist
108
and the field oxide film
102
as a mask, boron ions are implanted with an impurity density of about 7×10
12
/cm
2
onto channel areas of the transistors to control a threshold voltage of the first NMIS transistor (FIG.
37
).
In a similar manner as for the NMIS transistors, the third photoresist
108
is first removed and then phosphorus ion implantation is conducted with an impurity density of about 1×10
13
/cm
2
onto punchthrough stopper forming areas of the first and second PMIS transistors using fourth photoresist
110
and the field oxide film
102
as a mask. Using the fourth photoresist
110
and the field oxide film
102
as a mask, phosphorus ion implantation is conducted with an impurity density of about 7×10
12
/cm
2
onto channel areas of the transistors to control a threshold voltage of the first PMIS transistor (FIG.
38
).
Thereafter, the fourth photoresist
110
is removed. Using fifth photoresist
111
and the field oxide film
102
as a mask, boron ions are implanted with an impurity density of about 1×10
13
/cm
2
onto the second NMIS transistor forming area up to a depth of a channel area to control a threshold voltage of the second NMIS transistor (FIG.
39
).
The fifth photoresist
111
is then removed. Using sixth photoresist
112
and the field oxide film
102
as a mask, phosphorus ion implantation is conducted with an impurity density of about 1×10
13
/cm
2
onto the second PMIS transistor forming area up to a depth of a channel area to control a threshold voltage of the second PMIS transistor (FIG.
40
).
After removing the sixth photoresist
112
, a predetermined annealing step is conducted to activate a doped area
113
to control the threshold voltage of the first NMIS transistor, a doped area
114
to control the threshold voltage of the first PMIS transistor, a doped area
115
to control the threshold voltage of the second NMIS transistor, a doped area
116
to control the threshold voltage of the second PMIS transistor, a doped area
117
for a channel stopper of the first NMIS transistor, a doped area
118
for a channel stopper of the first PMIS transistor, a doped area
119
for a channel stopper of the second NMIS transistor, and a doped area
120
for a channel stopper of the second PMIS transistor.
The sacrificial oxidation film
103
is removed using hydrofluoric acid solution, and a gate insulation film
121
is then formed by thermal oxidation at about 850° C. (FIG.
41
). An about 200 nm thick polycrystalline silicon or polysilicon film
122
is deposited thereon by chemical vapor deposition (CVD) (FIG.
42
). Using seventh photoresist
123
as a mask, a phosphorus doping step is conducted with an impurity concentration of about 1×10
15
/cm
2
or more onto the film
122
of the NMIS transistor area (FIG.
43
). The seventh photomask
123
is then removed. Using eighth photoresist
124
as a mask, a boron doping step is conducted with an impurity concentration of about 1×10
15
/cm
2
or more onto the film
122
of the PMIS transistor area (FIG.
44
).
Through a predetermined annealing step, the polycrystalline silicon film
122
in the NMIS area becomes an n-type polycrystalline silicon film
123
and the polycrystalline silicon film
122
in the PMIS area becomes a p-type polycrystalline silicon film
124
. A barrier metal film
125
of, for example, wolfram nitride and a refractory metal film
126
of, for example, wolfram are sequentially deposited thereon by sputtering (FIG.
45
).
By photolithography and dry etching, gate electrode patterns are formed in the multilayer film or the lamination of the n-type polycrystalline silicon film
123
, the wolfram nitride layer
125
, and the wolfram layer
126
of the NMIS area as well as the lamination or the multilayer film of the p-type polycrystalline silicon film
124
, the wolfram nitride layer
125
, and the wolfram layer
126
of the PMIS area (FIG.
46
).
Finally, an arsenic ion implantation is conducted onto the NMIS area to produce an n-type highly doped area
127
and a boron ion implantation is conducted onto the PMIS area to produce a p-type highly doped area
128
(FIG.
47
).
SUMMARY OF THE INVENTION
In the CMIS transistor manufacturing method of the prior art as described above, six kinds of photoresist are required in the impurity doping steps for wells, channels, and gate areas. Additionally, when two types of threshold voltages are set respectively for the NMIS and for the PMIS, eight kinds of photoresist are required. Since many photolithography steps are necessary, a long period of time is required to manufacture the semiconductor integrated circuit device and the production cost is increased.
To solve the problem, there is provided according to one aspect of the present invention a method of manufacturing a semiconductor integrated circuit device including a semiconductor substrate and at least one first transistor having a first conductivity type and at least one second transistor having a second conductivity type opposite to the first conductivity type, the first and second transistors being formed on the semiconductor substrate. The method comprises a step of forming a gate insulating film on one surface of the semiconductor substrate, a step of depositing a gate material film using material for gates on the gate insulating film, a step of forming first photoresist covering a second area in which the second transistor is formed, the first photoresist having an opening in a first area in which the first transistor is formed; a step of conducting ion implantation using the first photoresist as a mask for formation of a well, threshold voltage control, and gate doping of the first transistor, a step of removing the first phot
Ikeda Shuji
Kamohara Shiro
Kimura Shin'ichiro
Kuroda Kenichi
Matsuoka Hideyuki
Cao Phat X.
Doan Theresa T.
Hitachi , Ltd.
Miles & Stockbridge P.C.
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