Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-06-30
1999-05-18
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438258, H01L21/8247
Patent
active
059045183
ABSTRACT:
A method of manufacturing a semiconductor memory device having nonvolatile memory cells of a single-element type. The method provides for the formation of a floating gate electrode insulatedly on a main surface of a semiconductor substrate and a control gate electrode on the floating gate via a second gate insulating film. Also by this method, an impurity, for example, arsenic, is introduced in self-alignment with the pair of opposing end sides of the control gate electrode to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. In accordance with the scheme, the first semiconductor region is formed to have a junction depth greater than the junction depth associated with the second semiconductor region and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Moreover, carriers which are stored in the floating gate electrode are transferred therefrom to the first semiconductor region, for example, during an erase operation of the memory, by tunneling through the insulating film beneath the floating gate electrode. The method also calls for the formation of MISFETs associated with peripheral circuitry of the memory.
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Kamigaki Yoshiaki
Komori Kazuhiro
Kume Hitoshi
Meguro Satoshi
Nishimoto Toshiaki
Chaudhari Chandra
Hitachi , Ltd.
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