Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
1999-08-24
2001-01-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C438S291000, C438S299000
Reexamination Certificate
active
06177303
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device with a field effect transistor, in which method a semiconductor body is provided, at a surface, with a source region and a drain region, while using a doping mask containing a polycrystalline silicon (hereinafter referred to as poly), and in which method subsequently a dielectric layer is provided which is subjected to a material-removing treatment, such as etching or polishing, to remove a part of its thickness, so that the poly-containing doping mask is exposed again, whereafter said poly-containing doping mask is removed by means of a selective etch step and, subsequently, a conductive layer is provided in the resultant recess in the dielectric layer, which conductive layer constitutes the gate of the transistor. Such a method is known, inter alia, from the article “Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process” by A. Chatterjee et. al., IEDM 97, pp. 821/824. The “replacement gate process” enables MOS transistors with a metal gate to be manufactured in a self-recording manner, instead of the customary polysilicon gates which have a much higher resistance.
In the known process, a dummy gate of polysilicon is formed in the same manner as the poly gate in standard CMOS processes. After the formation of the source and drain regions, an oxide layer which serves as the dielectric layer is deposited, whereafter the thickness of the dielectric layer is reduced down to the poly by means of chemico-mechanical polishing (hereinafter referred to as CMP). Subsequently, the poly of the dummy gate is removed by selective etching. The resultant recess in the oxide layer is filled by a metal gate of Al or W.
In practice it has been found that the reproducibility of this process is limited. In particular the point in time at which the chemico-mechanical polishing operation of the oxide layer is interrupted proved to be very critical. If the CMP is stopped too early, the remaining oxide makes it very difficult to remove the poly. If the CMP process is continued too long, then the height of the gate to be formed eventually proves to be ill-defined.
SUMMARY OF THE INVENTION
It is an object of the invention to provide, inter alia, a “replacement gate” process having a better reproducibility. To achieve this, a method of the type described in the opening paragraph is characterized in accordance with the invention in that the poly-containing doping mask is provided in the form of a double layer comprising a first sub-layer of polysilicon and a second sub-layer, which is provided on the first sub-layer and consists of a material having a greater resistance to the material-removing treatment than polysilicon, and which material can be selectively etched relative to said dielectric layer. The invention is based, inter alia, on the recognition that poly has a fairly low resistance to CMP, which is the reason why the point in time at which CMP is interrupted is so critical. By providing, in accordance with the invention, above said poly a layer of another material having a greater etch resistance than poly, the etch rate is reduced substantially when the second sub-layer is reached.
An important embodiment of a method in accordance with the invention is characterized in that the dielectric layer is formed by silicon oxide and the second sub-layer is formed by a layer containing silicon nitride.
REFERENCES:
patent: 5856225 (1999-01-01), Lee et al.
patent: 6015747 (2000-01-01), Lopatin et al.
patent: 6022783 (2000-02-01), Wu
patent: 6033963 (2000-03-01), Huang et al.
patent: 2757312A1 (1998-06-01), None
“Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process”, by A. Chatterjee et al, IEDM 97, p. 821-824.
Montree Andreas H.
Schmitz Jurriaan
Woerlee Pierre H.
Biren Steven R.
Le Dung A
Nelms David
U.S. Philips Corporation
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