Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-03-15
2011-03-15
Toledo, Fernando L (Department: 2895)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S625000, C438S626000, C438S627000, C438S628000, C438S629000, C438S637000, C438S687000, C438S691000, C257S203000, C257S620000, C257S750000, C257S752000, C257S773000, C257S774000, C257S777000, C257S797000, C257SE23011, C257SE21495, C205S123000, C205S137000, C029S846000, C029S847000, C029S852000
Reexamination Certificate
active
07906430
ABSTRACT:
A peeling prevention layer for preventing an insulation film and a protection layer from peeling is formed in corner portions of a semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.
REFERENCES:
patent: 5229647 (1993-07-01), Gnadinger
patent: 5399898 (1995-03-01), Rostoker
patent: 5424245 (1995-06-01), Gurtler et al.
patent: 5432999 (1995-07-01), Capps et al.
patent: 5561082 (1996-10-01), Matsuo et al.
patent: 5814889 (1998-09-01), Gaul
patent: 6168969 (2001-01-01), Farnworth
patent: 6570243 (2003-05-01), Hagihara
patent: 6710446 (2004-03-01), Nagai et al.
patent: 6809421 (2004-10-01), Hayasaka et al.
patent: 6998344 (2006-02-01), Akram et al.
patent: 7102219 (2006-09-01), Hanaoka et al.
patent: 7112863 (2006-09-01), Imaoka
patent: 7112887 (2006-09-01), Swan et al.
patent: 7122457 (2006-10-01), Tanida et al.
patent: 7122912 (2006-10-01), Matsui
patent: 7193239 (2007-03-01), Leedy
patent: 2002/0130412 (2002-09-01), Nagai et al.
patent: 2002/0170173 (2002-11-01), Mashino
patent: 2004/0063268 (2004-04-01), Noma et al.
patent: 2004/0147128 (2004-07-01), Yui et al.
patent: 1408547 (2004-04-01), None
patent: 2003-309221 (2003-10-01), None
Umemoto et al., U.S. Office Action, mailed May 15, 2007, directed to U.S. Appl. No. 11/236,881; 11 pages.
Umemoto et al., U.S. Office Action, mailed Oct. 3, 2007, directed to U.S. Appl. No. 11/236,881; 9 pages.
Kameyama Kojiro
Suzuki Akira
Umemoto Mitsuo
Dulka John P
Kanto Sanyo Semiconductors Co., Ltd.
Morrison & Foerster / LLP
Sanyo Electric Co,. Ltd.
Toledo Fernando L
LandOfFree
Method of manufacturing a semiconductor device with a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device with a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device with a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2654933