Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-15
2003-09-02
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S302000
Reexamination Certificate
active
06613634
ABSTRACT:
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. In particular, the invention pertains to a technique effective when applied to a semiconductor integrated circuit device with an SRAM (Static Random Access Memory) having a memory cell formed of 6 MISFETs (Metal Insulator Semiconductor Field Effect Transistor).
BACKGROUND OF THE INVENTION
As a cache memory for personal computers or work stations, an SRAM whose memory cell is made up of 6 MISFETs has been employed. Such an SRAM is described, for example, in Japanese Patent Application Laid-Open No. Hei 9(1997)-1129753, Japanese Patent Application Laid-Open No. Hei 9(1997)-55440, which is a Japanese application corresponding to U.S. Pat. No. 5,880,020, or Japanese Patent Application Laid-Open No. Hei 9(1997)-36252, which is a Japanese application corresponding to U.S. Pat. No. 5,780, 910.
Attempts to miniaturize an MISFET have met with the problem of lowering of the withstand voltage between source and drain due to short channel effects. More specifically, when the channel length (width of a gate electrode) becomes short with miniaturization of the MISFET, depletion layers extending from the source and drain, respectively, are linked inevitably. Under such a state, the drain field exerts an influence on the source and decreases the diffusion potential in the vicinity of the source so that a current flows between the source and drain even without a channel (punch through phenomenon). Once this punch through phenomenon occurs, the drain current undergoes a drastic increase with an increase in the drain voltage, thereby preventing the flow of saturation current.
With a view toward overcoming the above-described problem, a source and drain structure has been proposed which adopts an LDD structure (Lightly doped Drain) formed of a low-concentration semiconductor region and a high-concentration semiconductor region. In addition, by forming, below the source and drain, a region (which is called a pocket ion region or halo region) made of an impurity having a conductivity type opposite to that of the impurity of the source and drain, widening of each of the depletion layers extending from the source and drain is suppressed, whereby the appearance of a punch through phenomenon is prevented.
SUMMARY OF THE INVENTION
It is effective to form this pocket ion region not only below the source and drain, but also in the channel region. Since a gate electrode lies over the channel region, the pocket ion region must be formed by an oblique ion injection method.
An SRAM has six MISFETs in total, as described above, that is, two n channel type driver MISFETs, two n channel type transfer MISFETs and two p channel type load MISFETs. Of these, two n channel type driver MISFETs and two p channel type load MISFETs constitute a pair of CMOS inverters.
Upon ion injection for forming the above-described pocket ion region (which will hereinafter be called “pocket ion injection”), it is necessary to carry out pocket ion injection to the p channel type load MISFET while covering the n channel type driver MISFET and n channel type transfer MISFET with a resist film, thereby preventing the injection into the n channel type MISFET of the pocket ions (n type) for the p channel type MISFET. On the contrary, upon pocket ion injection to the n channel type driver MISFET and the n channel type transfer MISFET, it is necessary to cover the p channel type load MISFET with a resist film, thereby preventing the injection into the p channel type MISFET of the pocket ions (p type) for the n channel type MISFET.
In a region wherein the p channel type MISFET and n channel type MISFET are close to each other, pocket ions cannot be injected to a region shielded by a resist film. As will be described later in detail, an active region in which the p channel type MISFET is to be formed is disposed so that its distance S from the end portion of the resist film over the n channel type MISFET would be greater than the product of the thickness H of the resist film and the tangent of an ion injection angle &thgr; (S>Htan&thgr;). An active region in which the n channel type MISFET is to be formed is disposed similarly so that its distance S from the end portion of the resist film over the p channel type MISFET would be greater than the product of the thickness H of the resist film and the tangent of an ion injection angle &thgr; (S>Htan&thgr;).
The thickness H of the resist film or ion injection angle &thgr; are almost specified to satisfy the exposure accuracy of the resist material or characteristics of an MISFET, which inevitably defines the distance S is between the end portion of the resist film and the active region. It is therefore difficult to decrease the cell area.
Moreover, even if the active region is spaced apart from the end portion of the resist film by the above-described distance S, when the resist film is formed at a position deviated from a desired position that is owing to mask misregistration, a region not permitting pocket ion injection appears, resulting in fluctuations of the pocket ion concentration, thereby causing fluctuations in the threshold voltage Vth of the MISFET constituting the SRAM.
An object of the present invention is therefore to provide a technique for reducing the area of a semiconductor integrated circuit device, for example, an SRAM.
Another object of the present invention is to provide a technique for suppressing variations in the threshold voltage Vth of an MISFET constituting a semiconductor integrated circuit device, for example, an SRAM, thereby improving its characteristics.
The above-described objects and novel features of the present invention will be apparent from the description herein and the accompanying drawings.
Among the aspects and features of the invention disclosed by the present application, typical ones will next be summarized briefly.
(1) In accordance with the present invention, the impurity concentration of the second pocket ion region of each of the n-channel type MISFET and p-channel type MISFET for a memory cell is made lower than that of the second pocket ion region of the n-channel type MISFET and p-channel type MISFET for a peripheral circuit.
(2) The impurity concentration of the second pocket ion region of the n-channel type MISFET and p-channel type MISFET formed in a first region and a second region spaced apart therefrom by a first distance D
1
is made lower than that of the second pocket ion region of the n-channel type MISFET and p-channel type MISFET formed in a third region and a fourth region spaced apart therefrom by a second distance D
2
. By preventing injection of impurities from one direction among impurities injected from four directions, the impurity concentration in the second pocket ion region of the n-channel type MISFET and p-channel type MISFET formed in an MISFET for a memory cell or a region adjacent thereto can be made low and uniform, thereby preventing fluctuations in the threshold voltage Vth. In addition, area reduction can be attained.
(3) Upon forming a pocket ion region in the first region by oblique ion implantation, oblique ion implantation is conducted while disposing the first region within a distance Si, which is the product of the thickness H of the resist film and the tangent of an ion implantation angle &thgr;, from the end portion of the resist film formed over the second region, which prevents injection of impurities from one direction among impurities injected from four directions, thereby making it possible to prevent fluctuations in the threshold voltage Vth. In addition, a reduction in the area can be attained.
REFERENCES:
patent: 5372957 (1994-12-01), Liang et al.
patent: 5534449 (1996-07-01), Dennison et al.
patent: 5668770 (1997-09-01), Itoh et al.
patent: 5780910 (1998-07-01), Hashimoto et al.
patent: 5880020 (1999-03-01), Mano
patent: 9-36252 (1997-02-01), None
patent: 9-55440 (1997-02-01), None
patent: 9-129753 (1997-05-01), None
Ichinose Katsuhiko
Ootsuka Fumio
Pham Hoai
Pham Long
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