Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1995-05-12
1998-04-14
Dutton, Brian
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438286, H01L 218234, H01L 21336
Patent
active
057390614
ABSTRACT:
A method of manufacturing a BiCMOS apparatus including a DMOS is disclosed which reduces manufacturing steps, shortens manufacturing time and reduces manufacturing cost. A channel ion implanted layer is formed by implanting acceptor impurities from the surface of a P-type well 5. A poly-silicon gate electrode is formed on gate insulation film and local oxide film. Impurity ions are then implanted for forming P-type base region by employing the bipolar transistor process and by using the gate electrode as a mask. Then, side walls are formed at high temperature on both sides of the gate electrode by employing the CMOS process of forming the LDD structure. At the same time, the P-type base region is formed by diffusing the implanted impurity ions. An N.sup.+ -type source region is then formed self-aligned by employing the CMOS process for forming the N.sup.+ -type source and drain of the CMOS transistor and by using the gate electrode 10 as a mask for the self alignment.
REFERENCES:
patent: 4914047 (1990-04-01), Seki
8057, MOS Technologies for Smart Power and High-Voltage Circuits, (1987)Nov. Paris,France Rossel.
G. Dolny et al.: IEDM 88 pp. 796-799 (1988) "Complementary DMOS/BiCMOS Technology for power IC applications".
N. Fujishima et al.: Proc. 5th International Symposium on Power Semiconductor Devices and ICs (1993) "High packing density power Bi-CMOS technology and its application for a motor drive LSI".
Fujishima Naoto
Kitamura Mutsumi
Dutton Brian
Fuji Electric & Co., Ltd.
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