Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-04-16
2002-08-20
Ho, Hoai V. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06436812
ABSTRACT:
This application is a counterpart of, and claims priority to, Korean Patent Application No. 2000-74165, filed on Dec. 7, 2000, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to method of manufacturing a semiconductor device and semiconductor device manufactured thereby, and more particularly to method of manufacturing a semiconductor device using an anti-reflective layer and a self-aligned contact technique, and the resulting semiconductor device.
2. Description of the Related Art
As semiconductor devices become more densely integrated, techniques of forming self-aligned contact holes for electrically connecting different conductive layers become increasingly important. The use of a SAC (self-aligned contact) allows the amount of source and drain contact area to be reduced, thus allowing smaller devices to be constructed.
FIGS. 1
to
5
are flow diagrams showing the process steps of a conventional method of manufacturing a DRAM (dynamic random access memory) device using a self-aligned contact technique. Each figure shows a cell array area of a DRAM device.
In
FIG. 1
, a device isolation layer
3
is formed on a semiconductor substrate
1
to define an active and an inactive region. A gate insulating layer
5
, for example, a gate oxide layer, is formed on the active region of the semiconductor substrate
1
. Then, a conductive layer
7
, an etch stop layer
9
, a hard mask layer
11
, and an anti-reflective layer
13
are sequentially formed on the semiconductor substrate
1
on which the gate insulating layer
5
is formed. In order to define gate pattern, i.e., word lines, a first photoresist pattern
15
is formed on the anti-reflective layer
13
.
The etch stop layer
9
is formed of an insulating layer, for example, a silicon nitride layer, which has an etch selectivity with respect to a silicon oxide layer. The hard mask layer
11
is formed of an insulating layer, for example a CVD (chemical vapor deposition) oxide layer, which has an etch selectivity with respect to the conductive layer
7
. The anti-reflective layer
13
is composed of material that reduces irregular reflections and keeps them to a minimum during the photolithography process, for example, a silicon oxinitride layer formed by a plasma CVD process. It is known that silicon oxynitride formed by a plasma CVD process exhibits good anti-reflective characteristics. However, it is also known that the leakage current characteristic of the insulating layer formed by plasma CVD process is poor since it is porous compared with an insulating layer formed by a low-pressure CVD process.
In
FIG. 2
, the anti-reflective layer
13
, hard mask layer
11
and etch stop layer
9
are continuously etched using the photoresist pattern
15
as a mask. As a result, etch stop layer pattern
9
a,
hard mask layer pattern
11
a,
and anti-reflective layer pattern
13
a
are sequentially formed in order on the conductive layer
7
. Thereafter, the photoresist pattern
15
is removed.
In
FIG. 3
, gate electrode
7
a
is formed by selectively etching the conductive layer
7
under openings or gaps between the etch stop layer patterns
9
a.
At this time, the anti-reflective layer pattern
13
a
remains on the hard mask layer pattern
11
a.
Gate pattern
14
—comprising gate electrode
7
a,
the etch stop layer pattern
9
a,
the hard mask layer pattern
11
a,
and the anti-reflective layer pattern
13
a—
is formed on the gate insulating layer
5
. A gate pattern (not shown) is also formed on a peripheral circuit area of the semiconductor device.
A conformal spacer insulating layer
17
is then formed on the whole surface of the resultant structure on which the gate pattern
14
is disposed. An interlayer insulating layer
19
, for example a CVD oxide layer, is formed on the spacer insulating layer
17
.
In the peripheral circuit area, spacers (not shown) are formed on side walls of a gate pattern by anisotropically etching a spacer insulating layer in the peripheral circuit area, before the interlayer insulating layer
19
in the cell array area is formed. The spacers are not formed in the cell array area at the same time that they are formed in the peripheral circuit area, because the semiconductor substrate in the cell array area can be damaged due to the anisotropic etch process. If this etch damage occurs, the contact leakage current characteristic of a cell transistor is deteriorated, thereby causing a problem wherein the refresh period of the DRAM device is shortened. To solve this problem, a widely used technique forms spacers only on side walls of the gate pattern in the peripheral circuit area. Thereafter, a second photoresist pattern
21
is formed on the interlayer insulating layer
19
to define self-aligned contact holes.
In
FIG. 4
, self-aligned contact holes
23
are formed by an anisotropic etch process in which the interlayer insulating layer
19
, spacer insulating layer
17
and gate oxide layer
5
are continuously etched using the second photoresist patterns
21
as a mask so as to expose the semiconductor substrate under openings or gaps of the gate pattern
14
. The etch stop layer pattern
9
a
functions as an etch stop layer.
Accordingly, spacers
17
a
are formed on side walls of the etch stop pattern
9
a
and the gate electrode
7
a.
Also, edges of the hard mask layer pattern
11
a
and anti-reflective layer pattern
13
a
, which are disposed on the etch stop layer pattern
9
a
, can be etched. Thereafter, the second photoresist pattern
21
is removed.
In
FIG. 5
, a conductive layer, for example a polysilicon layer, is formed on the interlayer insulating layer
19
to fill in the self-aligned contact holes
23
. Conductive pads
25
are formed in the self-aligned contact holes
23
by completely etching the conductive layer and interlayer insulating layer
19
until the spacer insulating layer
17
on the gate pattern
14
is exposed. The anti-reflective layer pattern
13
a
remains between adjacent conductive pads
25
.
As is apparent from the foregoing description, in the conventional method of manufacturing a semiconductor device, the anti-reflective layer pattern
13
a
formed by a plasma CVD process remains between adjacent conductive pads
25
. Accordingly, the leakage current characteristic between conductive pads is deteriorated, thereby causing a problem wherein the refresh period of the DRAM device is shortened.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved method of manufacturing a semiconductor device which does not have an anti-reflective layer pattern, such as a porous insulating layer, between adjacent conductive pads, thereby improving the leakage current characteristic between adjacent conductive pads.
It is another object of the present invention to provide an improved semiconductor device itself which does not have an anti-reflective layer pattern, such as a porous insulating layer, between adjacent conductive pads, thereby improving the leakage current characteristic between adjacent conductive pads.
To achieve these and other objects, the present invention provides a method of manufacturing a semiconductor device using a self-aligned contact technique. The method includes steps of sequentially forming a gate insulating layer, a first conductive layer, an etch stop layer, a hard mask layer, and an anti-reflective layer on a semiconductor substrate, and then sequentially forming an etch stop layer pattern, hard mask layer pattern, and anti-reflective layer pattern by partially etching the etch stop layer, the hard mask layer, and the anti-reflective layer. The anti-reflective layer pattern can be formed of an inorganic anti-reflective layer or an organic anti-reflective layer.
The method further includes steps of etching the anti-reflective layer pattern and the first conductive layer to form a gate electrode under the etch stop layer pattern, forming a conformal spacer insulating layer on the whole surface of the semico
Ho Hoai V.
Le Thao P
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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