Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-08
2001-11-13
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000
Reexamination Certificate
active
06316300
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based upon Japanese Patent Application Nos. Hei. 10-261622 filed on Sep. 16, 1998 and Hei. 11-234006 filed on Aug. 20, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device, and especially to a method of manufacturing a semiconductor device having a step of selectively forming an oxide film by a thermal oxidation, and can be used for, for example, a method of manufacturing a power semiconductor device such as a vertical type MOSFET (Metal Oxide Semiconductor Field Effect transistor) or an IGBT (Integrated Gate Bipolar Transistor) in which a portion where the oxide film is formed is used as a channel forming region.
2. Related Art
A conventional vertical type power MOSFET having a concave structure is disclosed in Japanese Patent Application Laid-open No. Hei. 8-236766 (U.S. Pat. No. 5,776,812). According to this vertical type power MOSFET, a plurality of channel wells are formed on a surface of a semiconductor substrate, U-groove is formed in crosswise around the channel wells, and channel region is to be formed along sidewall of the U-groove of each channel wells. Here, the semiconductor substrate is formed by an N-type silicon substrate having an orientation of (100) and N-type epitaxial layer grown on the N-type silicon substrate. The channel wells are formed as P-type wells.
The manufacturing steps of such a vertical type MOSFET include the following steps. That is, it includes: mask forming step for forming a silicon nitride film having an opening having a grid-shaped pattern as a mask member on the semiconductor substrate at a region where the U-grove is to be formed; groove forming step for forming the grid-shaped U-groove on the semiconductor substrate by performing an isotropic etching (chemical dry etching) on the semiconductor substrate through the opening of the silicon nitride; oxide film forming step for forming a groove portion LOCOS oxide film to be filled in the U-groove by a thermal oxidation using the silicon nitride film as a mask; and channel well forming step for forming a channel well by implanting impurities by using the groove portion LOCOS as a mask by a self-alignment implantation.
In the conventional oxide film forming step, the groove portion LOCOS oxide film as a thick oxide film is formed by rapidly oxidizing a surface of the semiconductor substrate by a long time thermal oxidation under a relatively high temperature higher than 1000° C. (generally, 1050° C.). However, when such the oxide film forming step is adopted, as shown in
FIG. 7
, it is found that numerous pits corresponding to lattice defects are generated at peripheral regions of the channel wells (shown as “b”) of the U-groove (shown as “a”). These lattice defects cause decreasing of a yield of manufacturing the vertical type MOSFET. Here,
FIG. 7
is a schematic diagram showing a photograph of the surface of the semiconductor substrate wherein a Secco etching (K
2
Cr
2
O
7
=2.25 grams per HF=100 cc, H
2
O=50 cc) is performed after disposing the surface of the semiconductor substrate having passed each steps including the oxide film forming step (Note that the thermal oxidation in the oxide film forming step is a wet oxidation using a water vapor as an oxidizing agent). In
FIG. 7
, a line type pit “A” is caused by an OSF (Oxidation induced Stacking Fault), and a dot type pit “B” is caused by a dislocation.
It is estimated that the OSF is mainly caused by a heavy-metals pollution in a manufacturing equipment such as a dray etching reactor or an oxidation reactor, and dislocation is mainly caused by a thermal stress generated at regions corresponding to edge portions of the groove portion LOCOS oxide film in the semiconductor substrate during the thermal oxidation process.
Here, the OSF may be reduced by reducing heavy-metals to be attached in the reactor during the etching process of the semiconductor substrate, or thoroughly washing the semiconductor substrate before the thermal oxidation process, however, the dislocation can not be reduced by these measures.
SUMMARY OF THE INVENTION
This invention has been conceived in view of the background thus far described and its first object is to provide a method of manufacturing of a semiconductor device having a thermal oxidation process for selectively forming an oxide film by a thermal oxidation, which can reduce the generation of lattice defects in the semiconductor device during the thermal oxidation process.
According to the present invention, first wet oxidation step oxidizes a semiconductor substrate through an opening of a mask by a wet thermal oxidation at a first oxidation temperature; and second wet oxidation step further oxidizes the semiconductor substrate through the opening of the mask by a wet thermal oxidation at a second oxidation temperature higher than the first oxidation temperature. In this case, lattice defects due to dislocation are reduced because thermal stress generated at the semiconductor substrate where corresponding to an edges of a oxide film in the groove portion at the second wet oxidation step is largely released.
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Fukazawa Takeshi
Okabe Yoshifumi
Ozeki Yoshihiko
Yokura Hisanori
Denso Corporation
Le Dung A
Nelms David
Pillsbury & Winthrop LLP
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