Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-16
2002-09-24
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S359000, C438S424000
Reexamination Certificate
active
06455381
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to improvement of a manufacturing method of a semiconductor device having a miniature structure with trench isolation.
2. Background Art
In recent years, the demand for semiconductor devices has increased rapidly with marked spread of information equipment such as computers or the like. In terms of functionality, semiconductor devices having large memory capacity and capable of high-speed operation are required. To satisfy those demand and requirements, technical developments for increasing the integration density, the response speed, and the reliability of semiconductor devices are now being made.
The trench isolation as a device isolation method in semiconductor devices is effective for the device miniaturization because what is called bird's beak is less prone to be formed in the trench isolation than in the LOCOS isolation. A manufacturing method including trench isolation will be described below.
As shown in
FIG. 17
, patterns of a pad insulating film
2
(silicon oxide film), a polysilicon film
3
, and a silicon nitride film
4
are formed on a p-type silicon substrate
1
.
Then, as shown in
FIG. 18
, a trench
5
is formed by etching the silicon substrate
1
by using the silicon nitride film
4
as a mask. Alternatively, the silicon nitride film
4
, the polysilicon film
3
, the pad insulating film
2
, and the silicon substrate
1
may be etched at one time by using a resist mask.
Then, as shown in
FIG. 19
, after the trench
5
is filled in by depositing a silicon oxide film
6
by CVD, for example, the part of the silicon oxide film
6
above the silicon nitride film
4
is removed by CMP, for example. Part of the remaining silicon oxide film
6
is thereafter removed by using hydrofluoric acid, whereby the level difference is reduced.
Then, as shown in
FIG. 20
, the silicon nitride film
4
is removed by using phosphoric acid, for example.
Then, the polysilicon film
3
shown in
FIG. 20
is removed by using a plasma etching apparatus, whereby the pad insulating film
2
is exposed as shown in FIG.
21
.
Then, the pad insulating film
2
shown in
FIG. 21
is removed by using hydrofluoric acid, whereby the surface of the silicon substrate
1
is exposed as shown in FIG.
22
.
Then, as shown in
FIG. 23
, a gate insulating film
7
is formed, and a doped polysilicon film
8
, a metal silicide film
9
, and an insulating film
10
are formed thereon. Thereafter, a gate electrode is formed by patterning and etching the lamination films. A MOS transistor is thereafter formed by forming a pair of n-type source and drain regions
11
by ion implantation.
In the above manufacturing process, the thickness of the pad insulating film
2
has been reduced with the recent miniaturization of devices. As a result, the etching damage that occurs in removing the polysilicon film
3
on the pad insulating film
2
tends to encompass the silicon substrate
1
.
Where the trench-filling silicon oxide film
6
is formed by HDP-CVD, it has an overhang as shown in part A in FIG.
24
. This causes another problem that polysilicon etching residues
12
tend to occur as shown in
FIG. 25
when the polysilicon film
3
is etched.
Because of a small selective etching ratio of the polysilicon film
3
to the pad insulating film
2
, the thickness of the remaining pad insulating film
2
varies in its plane. Therefore, where an impurity for controlling the threshold voltage of the transistor is implanted in the state of
FIG. 21
, a problem occurs that the uniformity of the threshold voltage is low. This phenomenon is remarkable when the implantation energy is low.
Where the trench-filling silicon oxide film
6
is formed by HDP-CVD, for example, there is a problem that at the time of a heat treatment the thickness of the pad insulating film
2
is increased as denoted by reference numeral
19
in
FIG. 26
because of degassing from the silicon oxide film
6
(HDP-CVD film). This phenomenon is particularly remarkable in a wafer peripheral portion, and causes a problem that the uniformity of the threshold voltage is low in a case where an impurity for threshold voltage control is implanted.
There is another problem that if the above-mentioned heat treatment is performed in a nitriding atmosphere, the silicon substrate
1
is nitrided through the pad insulating film
2
. In particular, this phenomenon occurs in a case where the pad insulating film
2
has thin portions in the vicinity of the isolation oxide film
6
as shown in part B in FIG.
27
. And this phenomenon is particularly remarkable in a case where the pad insulating film
6
is formed again (a process of FIG.
21
→FIG.
22
→FIG.
21
). In nitrided regions, the thickness of the gate oxide film
7
is small and hence the gate breakdown voltage is low; that is, the reliability of the gate insulating film
7
is lowered.
FIGS. 28-31
show another problem of roughening of the trench portion. In each of
FIGS. 28-31
, the left-hand part shows a device portion (or a device forming portion) and the right-hand part shows a mark portion.
The conventional trench isolation has a problem that, because of a small level difference, alignment marks cannot be detected at ensuing steps. To solve this problem, after formation of the trench isolation structure, the portions other than mark portions are covered with a resist
21
(see
FIG. 28
) and then the silicon oxide film
6
that is buried in the trench portion
22
is removed only in the mark portions to form steps (see FIG.
29
). Then, an impurity for well formation or control of the threshold voltage of the transistor is implanted (see FIG.
30
). However, there is a problem that the portions where the silicon substrate
1
is exposed, in particular, the trench portions, are roughened in a heat treatment for activating the impurity (see FIG.
31
). The roughening may lower the alignment accuracy. It is considered that this phenomenon relates to the etching damage or stress that occurs at the time of the formation of the trench isolation structure. This phenomenon is particularly remarkable in a case where the trench isolation structure is formed in a high-temperature, non-oxidizing atmosphere.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems in the art, and an object of the invention is therefore to increase the reliability of a gate oxide film and improve the junction leak characteristic by wet-removing a silicon film on an insulating film or optimizing treatment/film-forming steps in a trench isolation process.
According to one aspect of the present invention, in a method of manufacturing a semiconductor device,
a pad insulating film, a polysilicon film, and a silicon nitride film are formed sequentially on a semiconductor substrate. A trench portion for isolating device forming regions on the semiconductor substrate is formed by selectively etching the silicon nitride film, the polysilicon film, the pad insulating film, and the semiconductor substrate. A silicon oxide film is embedded in the trench portion for isolating the device forming regions. The silicon nitride film, the polysilicon film, and the pad insulating film are removed to expose a surface of the semiconductor substrate. Then, a circuit element is formed on the exposed surface of the semiconductor substrate. Particularly in the above method, the polysilicon film is removed by isotropic wet etching.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device, at least a gate insulating film, a polysilicon film, and an upper insulating film are sequentially formed on the exposed surface of the semiconductor substrate as described above, and a gate electrode is formed by patterning the upper insulating film, the polysilicon film, and the gate insulating film by anisotropic etching. Then, isotropic wet etching is performed to remove polysilicon on the surface of the semiconductor substrate.
According to still another aspect of the present inve
Fujiishi Yoshitaka
Shimizu Masahiro
Gurley Lynne A.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Niebling John F.
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