Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-15
2003-04-08
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S291000, C438S303000
Reexamination Certificate
active
06544851
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body of a first conductivity type which is provided at a surface with a transistor having a gate insulated from a channel provided at the surface of the semiconductor body by a gate dielectric.
Such a method is known from U.S. Pat. No. 5,534,447. In the known method a shielding layer of, for example, silicon oxide provided with an opening is applied to the surface of the semiconductor body of the first conductivity type, the opening having side walls defining the channel of the transistor. The side walls of the opening are provided with side wall spacers of, for example, silicon nitride. The surface of the semiconductor body, which is confined by the side wall spacers, is provided with the gate dielectric, to which a conductive layer of, for example, polycrystalline silicon is applied providing the gate of the transistor. The side wall spacers are then removed, thereby forming trenches which are confined by the gate and the shielding layer, via which trenches impurities of the first and a second, opposite conductivity type are introduced into the semiconductor body. The shielding layer is removed and the surface of the semiconductor body is provided with a source zone and a drain zone of the second conductivity type.
A disadvantage of the known method is that the introduction of the impurities via the trenches takes place prior to the formation of the source zone and the drain zone. As the formation of the source zone and the drain zone is associated with a high-temperature anneal with temperatures as high as about 1000° C., the impurities previously introduced via the trenches are adversely redistributed, which adversely affects the performance of the transistor.
SUMMARY OF THE INVENTION
It is an object inter alia of the invention to provide a method of manufacturing a semiconductor device, which allows a local introduction of impurities via the trenches into the semiconductor body without adversely redistributing the locally introduced impurities in a later stage of the process.
According to the invention, this object is achieved in that a structure is provided on the surface, which structure comprises a dielectric layer having a recess, which recess is aligned to a source zone and a drain zone of a second conductivity type provided at the surface of the semiconductor body and has side walls extending substantially perpendicularly to the surface of the semiconductor body, in which recess a double-layer is applied consisting of a second sub-layer on top of a first sub-layer, which second sub-layer is removed over part of its thickness until the first sub-layer is exposed, which first sub-layer is selectively removed with respect to the second sub-layer and the side walls of the recess to a depth, thereby forming trenches extending substantially perpendicularly to the surface of the semiconductor body, via which trenches impurities of the first conductivity type are introduced into the semiconductor body, thereby forming pocket implants.
The above-stated measures in accordance with the invention prevent the impurities, which have been locally introduced into the semiconductor body via the trenches, from being exposed to the high temperatures of the anneal associated with the formation of the source zone and the drain zone. In this way, a redistribution of the locally introduced impurities is counteracted.
The structure comprising the dielectric layer having the recess aligned to the source zone and the drain zone may be obtained by providing the surface of the semiconductor body with a source zone and a drain zone, and subsequently providing it with a dielectric layer having a recess aligned to the source zone and the drain zone. Clearly, a large accuracy is needed to make sure that the recess is provided so as to be aligned to the source zone and the drain zone. A preferred embodiment of the method in accordance with the invention is therefore characterized in that, in order to provide the structure, a patterned layer is applied at the area of the planned gate, and the source zone and the drain zone of the second conductivity type are formed in the semiconductor body while using the patterned layer as a mask, after which the dielectric layer is provided in such a way, that the thickness of the dielectric layer next to the patterned layer is substantially equally large or larger than the height of the patterned layer, which dielectric layer is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, after which the patterned layer is removed, and the recess is provided so as to be aligned to the source zone and the drain zone. In this way, the recess is provided in a self-aligned way with respect to the source zone and the drain zone. Further advantageous embodiments of the method in accordance with the invention are described in other dependent claims.
REFERENCES:
patent: 4173818 (1979-11-01), Bassous et al.
patent: 5534447 (1996-07-01), Hong
patent: 5899719 (1999-05-01), Hong
patent: 5940710 (1999-08-01), Chung et al.
patent: 5960270 (1999-09-01), Misra et al.
“Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement gate Process”, by A. Chatterjee et al., IEDM 1997, pp. 821-824.
Dachs Charles Johan Joachim
Ponomarev Youri
Webster Marian Nelia
Koninklijke Philips Electronics , N.V.
Tsai Jey
Waxler Aaron
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