Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-22
2004-02-24
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S528000, C438S525000, C438S302000
Reexamination Certificate
active
06696341
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the improvement of the semiconductor device having the electrostatic discharge (hereinafter referred to as “ESD”) resistance of an ESD protection element that protect an internal circuit from the breakdown due to an ESD.
2. Description of the Background Art
An integrated circuit is usually provided with a protection circuit in order to protect an internal circuit from the breakdown due to ESDs, such as discharge of the charge from the exterior, and discharge of the charge charged to the integrated circuit. An ESD protection element that comprises an MOS transistor or a field transistor utilizing a local oxidation of silicon (hereinafter referred to as “LOCOS”) oxide film is used as a protection circuit. Generally, one electrode of a transistor serving as an ESD protection element is connected an I/O terminal, and the other electrode is connected to a fixed potential setting terminal, e.g., a ground terminal.
FIG. 25
is a circuit diagram showing a connection example of an NMOS transistor for protection. As shown in
FIG. 25
, the drain of an NMOS transistor for protection Q
1
is connected to an I/O terminal P
1
, and the source and gate are grounded. An internal circuit (not shown) for performing the actual operation is also connected to the I/O terminal P
1
.
When the normal voltage is applied to the I/O terminal P
1
, the NMOS transistor for protection Q
1
is in OFF state, causing no influence on the internal circuit. On the other hand, when an ESD occurs and the surge voltage SV is applied to the I/O terminal P
1
, the PN junction between an N type drain region and a P type well region (substrate) results in breakdown to discharge the surge voltage from the I/O terminal P
1
to a ground level (grounding terminal), thereby protecting the internal circuit.
A field transistor has the structure in which an LOCOS oxide film is provided in place of the gate section (i.e., the gate oxide film and gate electrode) of an MOS transistor. Therefore, such a field transistor does not maintain the original transistor structure, but it is called field transistor in the technical fields that deal with ESD. Hereinafter, the regions of a field transistor which correspond to the drain and source regions of an MOS transistor are also referred to as drain and source regions, respectively.
An N type field transistor for protection (whose drain and source regions are of the N type) having the above-mentioned structure may be connected in the same manner as in the NMOS transistor for protection Q
1
shown in FIG.
25
. However, no potential setting is required for a LOCOS oxide film.
Like the MOS transistor for protection, in the field transistor for protection, no current follows between the drain and source in the normal state, and when an ESD occurs, the PN junction between the N type drain region and the P type well region results in breakdown so that a surge voltage is discharged from an I/O terminal P
1
to a ground level (grounding terminal), to protect an internal circuit.
That is, the breakdown of the PN junction of an ESD protection element in the occurrence of an ESD allows the surge voltage to be discharged through the ESD protection element, thereby protecting the internal circuit. In prior art, an ESD protection element has been formed together with an internal circuit on a single semiconductor substrate under the same conditions.
However, as the refinement of elements is advanced, the ESD resistance of an ESD protection element is lowered, and therefore, even if an ESD protection element is formed inside an integrated circuit, failing to protect the breakdown due to an ESD.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor device having an ESD protection element comprises: a semiconductor substrate of a first conductivity type mainly composed of a first material; a first semiconductor region of a second conductivity type, formed in a surface of the semiconductor substrate; a second semiconductor region formed in a surface of the semiconductor substrate, independently of the first semiconductor region, edge portions in the first and second semiconductor regions opposed to each other being defined as first and second edge regions, respectively; and a semiconductor region for ESD protection of the first conductivity type, formed in a region of the semiconductor substrate including at least a region in the vicinity of a junction with the first and second edge portions, the semiconductor region for ESD protection being mainly composed of a second material having a smaller breakdown field than the first material.
According to a second aspect, the semiconductor device having the ESD protection element of the first aspect further comprises: an insulting film on the semiconductor substrate between the first and second semiconductor regions; and a gate electrode on the insulating film.
According to a third aspect, the semiconductor device having the ESD protection element of the first aspect further comprises an isolated insulating region, some of which projects from the semiconductor substrate between the first and second semiconductor regions, and the rest is buried in a surface of the semiconductor substrate.
According to a fourth aspect, the semiconductor device having the ESD protection element of the first aspect is characterized in that the semiconductor region for ESD protection is selectively formed in an upper portion of the semiconductor substrate; and the first edge portion of the first semiconductor region and the second edge portion of the second semiconductor region are formed in the semiconductor region for ESD protection.
According to a fifth aspect, the semiconductor device having the ESD protection element of the fourth aspect is characterized in that the semiconductor region for ESD protection includes first and second partial semiconductor regions for ESD spaced from each other in an upper portion of the semiconductor substrate; and the first edge portion is formed in the first partial semiconductor region for ESD, and the second edge portion is formed in the second partial semiconductor region for ESD.
According to a sixth aspect, the semiconductor device having the ESD protection element of the fourth aspect further comprises a preliminary semiconductor region mainly composed of a specific material, interposed between the semiconductor substrate and the semiconductor region for ESD protection, the specific material containing a mixture of the first material and the second material.
According to a seventh aspect, a method of manufacturing a semiconductor device having an ESD protection element comprises the steps of: (a) preparing a semiconductor substrate of a first conductivity type mainly composed of a first material; (b) selectively forming a semiconductor region for ESD protection mainly composed of a second material, in an upper portion of the semiconductor substrate, the second material having a smaller breakdown field than the first material; and (c) forming first and second semiconductor regions of a second conductivity type independently of each other in a surface of the semiconductor substrate including the semiconductor region for ESD protection, the step (c) forming first and second edge portions opposed to each other in the semiconductor region for ESD protection, the first and second edge portion being edge portions of the first and second semiconductor regions, respectively.
According to an eighth aspect, the method of the seventh aspect is characterized in that: the step (b) includes performing an ion implantation of a specific material having a smaller breakdown field than the first material in an upper portion of the semiconductor substrate, to form the semiconductor region for ESD protection mainly composed of a mixture of the specific material and the first material; and the second material contains the mixture.
According to a ninth aspect of the present invention, in the method of the eighth aspect, the semiconductor
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corp.
Wilczewski Mary
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