Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-19
2001-01-09
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S262000, C438S307000, C438S529000, C257S335000
Reexamination Certificate
active
06171912
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body including a field effect transistor, whereby a source region and a drain region are formed in the semiconductor body to form said transistor, and on the semiconductor body a gate region is formed above a channel region situated between the source region and the drain region, said gate region being formed by providing the semiconductor body with an (electrically) insulating layer, which is provided with a stepped portion in the thickness, whereafter the surface of the semiconductor body is provided with a. conductive layer which is removed again by etching, whereby a portion of the conductive layer, which lies against the stepped portion and which forms part of the gate region, remains intact. The invention also relates to a transistor which can be manufactured by such a method. Such a method is particularly suitable for the manufacture of discrete field effect transistors operating at a high frequency and, as in the case of a LDMOST (Lateral Double diffused Metal Oxide Semiconductor Transistor) having a high breakdown voltage. Such discrete field effect transistors can be used in an amplifier or driver stage for TV transmitters operating at a supply voltage of, for example, 28 V.
A method of the type mentioned in the opening paragraph is disclosed in U.S. Pat. No. 3,846,822, published on May 11, 1974. In said document a description is given of a method of manufacturing a DMOS transistor, in which a semiconductor body is provided with an insulating layer having a stepped portion in the thickness, in this case two stepped portions on either side of a strip-shaped mesa formed in the insulating layer. This insulating layer is provided with a conductive tungsten layer, the major part of which is removed again by etching. Making use of the shadow of the strip-shaped mesa, a part of the tungsten layer which is situated against a side face of the mesa is deliberately left intact in this etching operation. Said part forms the gate region of the transistor to be formed. Subsequently, a source region and a drain region of the transistor are formed on either side of the mesa, which serves as a mask. In a similar manner, also a part of the channel region of the transistor, which is situated below the gate region, is provided with a higher doping concentration. Finally, the source, gate and drain regions are provided with electrical connections.
A drawback of the known method is that, notwithstanding the low (electric) resistance of the gate region, also at a very short length, the use of metals proves to be very objectionable in practice. A gate region of polycrystalline silicon does not have these drawbacks and, of itself, also yields better transistors. However, ii is difficult to provide such a gate region with a sufficiently low resistance.
SUMMARY OF THE INVENTION
Therefore, it is an object of the invention to provide a method of manufacturing transistors with an excellent high-frequency behavior and hence a short gate region having a low resistance.
To achieve this, a method of the type mentioned in the opening paragraph is characterized in accordance with the invention in that the source region and the drain region are formed before the application of the insulating layer and after the application of the portion of the gate region formed from the conductive layer, the surface of the semiconductor body being made flat by applying a further insulating layer next to the stepped portion. The invention is based on the realization that in order to provide a very narrow gate region with a sufficiently high conductance, it is desirable to employ a gate region which is built up of two parts: first of all the part formed by the conductive layer, which preferably comprises polycrystalline silicon, and subsequently, an overlying part composed of a different, i.e. better conductor, for example a metal. The invention is further based on the realization that such an upper part of the gate region can be readily embodied so as to be sufficiently wide and well aligned, by making the structure comprising the lower portion of the gate region flat. In accordance with the invention, this is achieved by applying, after the formation of the lower portion of the gate region, a further insulating layer next to the stepped portion. Since the source and the drain are already formed before the insulating layer and the further insulating layer are provided, the stepped portion in the insulating layer does not have to serve as a mask to form the source and the drain. This enables not only a relatively thick (further) insulating layer to be applied but also a different shape and position of the stepped portion with respect to the known method. Also the latter has important advantages, as will be described more fully later.
In a preferred embodiment of a method in accordance with the invention, the stepped portion in the thickness of the insulating layer is formed by providing the insulating layer with a recess a side wall of which is situated above the channel region, thus forming the stepped portion, and another side wall forming a further stepped portion is situated above the source region. Since a recess (or aperture) in the insulating layer only has a local character, the semiconductor body can be readily made flat again after the formation of the portion of the gate region formed from the conductive layer. A recess further enables the transistor structure to be provided with advantageous constructive characteristics. For example, an extension of the source region can be readily formed through the recess, the remaining portion of the insulating layer serving as a mask. The same applies to a local increase of the doping concentration of the channel range, which is necessary for a DMOS transistor.
The choice of a recess in the insulating layer and the position thereof also relates to a further surprising realization which forms part of the invention. When a part of the gate region is formed against a side wall of the recess, a similar region is also formed against the other side wall of the recess. The above-mentioned realization is that, by virtue of the above-mentioned position of said further stepped portion, the removal of this “parasitic” gate region is not necessary because the presence thereof in an electrically insulating layer and above the source region does not have adverse effects.
Preferably, the semiconductor body which is made flat again is provided with another insulating layer in which contact apertures are made. Subsequently, a further conductive layer is provided, and the gate region is formed from this layer and the portion of the conductive layer lying against the stepped portion. In this manner, a gate region is readily formed, which may have, on the one hand, a very short length, i.e. the thickness of the conductive layer, and, on the other hand, a very low conductance, i.e. a conductance which is reduced by the further conductive layer. Preferably, polycrystalline silicon is used as the material for the conductive layer, and for the further conductive layer use is preferably made of a metal, such as aluminium, or a metal silicide, such as titanium silicide, which are materials having a much lower resistivity than polycrystalline silicon and, in addition, they can be used as a connection conductor.
In an attractive variant of a method in accordance with the invention, prior to the application of the conductive layer, a further recess is formed in the insulating layer and, after the application of the conductive layer, the part thereof which is situated in the further recess is masked during etching the conductive layer. Thus this variant enables a transistor having a so-called screening electrode to be obtained in a simple manner. This electrode can be used to preclude or, at least, reduce capacitive feedback from the drain region to the gate region.
Preferably, both the conductive layer and the further insulating layer are provided by means of uniform depo
Biren Steven R.
Pham Long
U.S. Philips Corporation
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