Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-27
2001-01-23
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S302000, C438S306000, C438S682000
Reexamination Certificate
active
06177314
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body of silicon which is provided at a surface with a field effect transistor with an isolated gate electrode, which surface is covered with a gate-dielectric layer on which a silicon layer is deposited, whereon an etch mask is formed which defines the gate electrode, whereafter the gate electrode is formed from the silicon layer by means of etching, after which doped regions are provided next to the gate electrode by implanting ions at the surface of the semiconductor body, which regions form a source region and a drain region of the transistor, whereafter, in a next step, a metal layer is applied which forms a contact with the source and drain regions in the semiconductor body and with an upper surface of the gate electrode and which is separated from the side walls of the gate electrode by an intermediate electrically insulating layer covering the side walls of the gate electrode, whereafter, by means of heating, metal silicide contacts are formed at locations where the metal layer contacts silicon and, subsequently, non-converted parts of the metal layer are removed by selective etching.
Such a method is disclosed, inter alia, in the patent document U.S. Pat. No. 5,753,557. In the manufacture of integrated circuits, the source and drain regions formed, as well as the gate electrode, are customarily provided with low-impedance contacts of a metal-silicon alloy, hereinafter referred to as silicide. The provision of these silicide contacts customarily takes place in a self-aligning manner by depositing a suitable metal, such as Ti, throughout the surface and subsequently carrying out a heating step. At the location where the Ti directly contacts the silicon, such as on the source and drain regions of the transistors and on the gate electrodes which are customarily made of doped polysilicon, the titanium is converted to silicide. At the location where titanium does not contact silicon, such as above field oxide or above groove-isolations, and on the spacer-covered side faces of the gate electrodes, the titanium is not converted. The unconverted titanium can be removed in a selective etching step. In practice it has been found that this often leads to a short-circuit between the source region and/or the drain region, on the one hand, and the gate electrode, on the other hand, via a connection along the spacers. In the literature, this phenomenon is often referred to as “bridging”. To preclude this short-circuit, it has already been proposed in the above-mentioned patent document U.S. Pat. No. 5,753,557 to extend the spacers on the gate electrode as far as the upper surface of the gate electrode, so that the distance between the silicide contacts is increased. A drawback of this method is, inter alia, that the contact on the gate electrode is reduced in size and hence the input resistance of the transistor is increased. In addition, this method requires a rather critical etching step to obtain the mask defining the contact on the gate electrode.
SUMMARY OF THE INVENTION
It is an object of the invention to provide, inter alia, a method wherein “bridging” is precluded without it causing an increase of contact resistances and without introducing additional critical process steps. To achieve this, a method of the type mentioned in the opening paragraph is characterized in accordance with the invention in that the implantation of ions is carried out in the presence of the etch mask on the gate electrode and at an angle with the normal to the surface such that ions incident on a side wall of the etch mask are scattered towards the surface of the semiconductor body and form sub-regions in the source and drain regions next to the gate electrode, which sub-regions have a higher doping level than parts of the source and drain regions which are situated at a greater distance from the gate electrode, whereafter, by means of thermal oxidation, an oxide layer is formed on the source and drain regions, which oxide layer has a greater thickness on the sub-regions than on the above-mentioned more distant parts of the source and drain regions, after which an etching step is subsequently carried out wherein the oxide layer on said more remote parts of the source and drain regions is entirely removed and the oxide layer on said sub-regions is removed only over a part of the thickness, so that an oxide layer remains above the sub-regions, and in a subsequent step, the metal layer is provided which, on said more remote parts, makes contact with the surface of the semiconductor body and, at the location of said sub-regions, is separated from the surface by the oxide layer. The invention makes use of the phenomenon, which is known per se, that in the case of oxidation of silicon, the oxidation rate increases with the doping concentration. As a result of ion scattering at the mask, the doping concentration in small areas close to the gate electrode is additionally increased, so that, in the case of oxidation, a thicker oxide grows above these areas, which forms an additional spacer during the silicidation process. These spacers are obtained in a simple and self-aligning manner without additional critical process steps.
Favorable embodiments of a method in accordance with the invention are described in the dependent claims.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
REFERENCES:
patent: 5508539 (1996-04-01), Gilbert et al.
patent: 5753557 (1998-05-01), Tseng
patent: 5891774 (1999-04-01), Ueda et al.
patent: 6074900 (2000-06-01), Yamazaki et al.
Druijf Klaas G.
Heessels Adrianus C. L.
Van Der Meer Hendrik H.
Biren Steven R.
Chaudhuri Olik
Doan Theresa T.
U.S. Philips Corporation
LandOfFree
Method of manufacturing a semiconductor device comprising a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device comprising a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device comprising a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2534630