Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-07
2001-03-06
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S346000, C257S365000, C257S401000, C438S163000, C438S180000, C438S217000, C438S525000
Reexamination Certificate
active
06198128
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, and semiconductor device technology. More particularly, it relates to techniques which are effective when applied to a method of manufacturing a semiconductor device and semiconductor device technology wherein field effect transistors are provided on a semiconductor substrate.
BACKGROUND OF THE INVENTION
It is effective to reduce the dimensions of field effect transistors, for enhancing the packaging density and driving capabilities thereof. In recent years, therefore, the microfabrication of the field effect transistors has been rapidly promoted. On the other hand, however, a supply voltage to each of the field effect transistors remains constant, and hence, the intensity of an electric field within the element increases. This has resulted in the occurrence of problems exerting bad influences on the characteristics of the element, such as a short channel effect. The short channel effect is a phenomenon in which, due to reduction in the channel length of the field effect transistor, the drain voltage of the transistor affects even a part lying directly under the gate electrode thereof, so that the potential of the surface of a semiconductor substrate is lowered to incur various evil effects such as fluctuation (fall) in the threshold voltage of the transistor and decrease in the effective channel length thereof. When the short channel effect has intensified more, so-called “punch-through” in which the drain current of the transistor fails to be controlled by the gate voltage thereof takes place to pose the problem of increase in the leakage current between the source and drain of the transistor. It has been known that the punch-through gives rise to degradation in the retention of storage in, for example, the transfer gate of a DRAM (Dynamic Random Access Memory). A technique which has been studied for avoiding the problems is, for example, one wherein in order to suppress the short channel effect, heavily-doped semiconductor regions (hereinbelow, termed “pocket regions”) of the same conductivity type as that of the impurity of the channel of a field effect transistor are provided at those end parts of the source region and drain region of the transistor which are near to the channel. Incidentally, a technique for providing the pocket regions is stated in, for example, U.S. Pat. No. 5,780,328.
SUMMARY OF THE INVENTION
As stated above, the provision of pocket regions is generally effective for ensuring the operating reliability of a micro field effect transistor. The inventors, however, have found out the problem that the adoption of such a structure hinders the highly dense arrangement of elements and wiring lines due to packaging densities heightened more and more or the change of the structure of a gate electrode.
Concretely, when the interval of adjacent elements is very narrow in the case of providing the pocket regions, an impurity for suppressing the short channel effect, which is to be introduced into a region for forming a field effect transistor between the adjacent elements is hampered by the gate electrode of another field effect transistor adjoining the first-mentioned transistor, and it fails to reach that part of a semiconductor substrate which underlies the end part of the gate electrode of the first-mentioned field effect transistor. With the technique for introducing the short-channel-effect suppressing impurity, accordingly, the interval of the gate electrodes adjacent to each other must be widened to some extent. In particular, a structure wherein each gate electrode is constituted by a plurality of conductor films or is overlaid with a cap insulator film has been adopted in recent years. In that case, the gate electrode (including the cap insulator film) becomes higher, and hence, the interval of the gate electrodes adjacent to each other is inevitably widened more. Besides, the layout of direct peripheral circuits, for example, sense amplifiers in a DRAM is determined by the layout pitch of memory cells. Therefore, the machining dimensions and layout intervals of the direct peripheral circuits must be set smaller than those of other peripheral circuits and logic circuits formed on the identical semiconductor substrate. Accordingly, the implantation of impurity ions for forming the pocket regions becomes difficult, and the further microfabrication of the elements is hindered.
Besides, the inventors made investigation into known examples of a technique for introducing an impurity for the suppression of the short channel effect, on the basis of the result of the present invention. Then, it has been found that the technique of this sort is stated in, for example, the official gazette of Japanese Patent Laid-open No. 350040/1994. The technique disclosed here is such that, before the impurity for suppressing the short channel effect is introduced into a semiconductor substrate, a photoresist film having openings by which gate electrodes and the surroundings are denuded is provided so as to prevent the short-channel-effect suppressing impurity from being introduced into the regions of the semiconductor substrate within predetermined ranges from the gate electrodes, owing to the photoresist film and the gate electrodes. In this way, transistors each having pocket layers and transistors each having no pocket layers are formed to endow the transistors with different threshold voltages in accordance with the presence or absence of the pocket layers.
An object of the present invention is to provide a technique which can enhance the packaging density of elements without incurring degradation in the performances of field effect transistors.
The above and other objects and novel features of the present invention will become apparent from the description of this specification when read in conjunction with the accompanying drawings.
Fundamental and typical aspects of performance of the present invention are briefly summarized as follows:
A method of manufacturing a semiconductor device according to the present invention consists in that, owing to the shadowing effect of gate electrodes adjacent to each other, an impurity for suppressing the short channel effect of field effect transistors is prevented from being introduced into the part of a semiconductor substrate as lies between the gate electrodes adjacent to each other.
According to the present invention, a method of manufacturing a semiconductor device wherein a semiconductor substrate is provided with a plurality of field effect transistors, comprises the steps of:
(a) forming gate electrodes of the plurality of field effect transistors on the semiconductor substrate, the gate electrodes including a first gate electrode which has a first side as well as a second side crossing the first side, and a second gate electrode which has a third side as well as a fourth side crossing the third side; and
(b) thereafter introducing an impurity into and aslant said semiconductor substrate, the impurity serving to suppress a short channel effect of said field effect transistors;
said first gate electrode and said second gate electrode being formed in a state where they are adjacent to each other with the first side and the third side confronting each other, in order that said impurity for suppressing the short channel effect, which is entered into said semiconductor substrate in first directions crossing said first side and said third side when viewed in plan, may be hindered by said first gate electrode and said second gate electrode from being introduced into a first region of said semiconductor substrate as lies between said first gate electrode and said second gate electrode.
In addition, according to the present invention, a method of manufacturing a semiconductor device wherein a semiconductor substrate is provided with a plurality of field effect transistors, comprises the steps of:
(a) forming gate electrodes of the plurality of field effect transistors on the semiconductor substrate, the gate electrodes including a
Asakura Hisao
Hyoma Masahiro
Miyamoto Masafumi
Miyatake Shin-ichi
Nagai Ryo
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Wojciechowicz Edward
LandOfFree
Method of manufacturing a semiconductor device, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2498878