Method of manufacturing a semiconductor device, and semiconducto

Details Method of manufacturing a semiconductor device, and semiconducto Method of manufacturing a semiconductor device, and semiconducto

1997-03-06

1998-07-28

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438302, H01L 218234

Patent

active

057862524

ABSTRACT:
A deep diffusion of the back-gate region provided in a self-aligned manner with respect to the gate electrode is necessary in a DMOS transistor for obtaining a sufficiently high punch-through voltage between source and drain. The combination of a comparatively heavy back-gate implantation and a light source implantation and a heavy source implantation with spacer on the gate electrode, and the use of interstitial diffusion and accelerated diffusion owing to crystal damage render it possible to carry out said diffusion of the back-gate region at a comparatively low temperature, for example below 950 .degree. C. This renders it possible to integrate a DMOST into, for example, standard VLSI CMOS where first .delta.V.sub.th and channel-profile implantations are carried out, and subsequently the poly gates are provided, which means that a diffusion step at a temperature above 1,000 .degree. C. of long duration is no longer allowed. The effect may be enhanced in that the doping of the back-gate region is increased during the p-type LDD implantation of a p-channel MOS and/or the p-type well implantation of an n-channel MOS.

REFERENCES:
patent: 4329186 (1982-05-01), Kotecha et al.
patent: 5156989 (1992-10-01), Williams et al.
patent: 5550067 (1996-08-01), Kuroyanagi et al.
patent: 5618743 (1997-04-01), Williams et al.
patent: 5674762 (1997-10-01), See et al.

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