Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-16
2003-07-29
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000
Reexamination Certificate
active
06599794
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-217226, filed Jul. 17, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device. In particular, the invention relates to a technology of forming an electrode using an electroplating method.
2. Description of the Related Art
SRAM (Static Random Access read write Memory) and EEPROM (Electrically Erasable and Programmable Read Only Memory) store an information by the combination of transistors. Moreover, a DRAM (Dynamic Random Access Memory) stores an information by the combination of transistor and capacitor. The integrated circuit of the above memory is realized by the combination of a MOS transistor and a MOS capacitor. However, a cell area is reduced; for this reason, it is difficult to realize the above integrated circuit by the combination of a transistor and a capacitor.
In particular, an S/N ratio (Signal to Noise ratio) of the capacitor should not be reduced even if the maximum (critical) micro-fabricating dimension becomes small. For this reason, there is a need of continuing to obtain a constant capacitance of capacitor. In order to obtain enough capacitance of capacitor, functional material thin films such as Ta
2
O
5
, SrTiO
3
, Ba
X
Sr
1−X
TiO
3
(BST) and PbZr
X
Ti
1−X
O3 (PZT) have been employed as a capacitor dielectric film. The functional material thin film shows a higher permittivity than a silicon oxide film, silicon nitride film/silicon oxide film laminated film (NO film). Recently, a device such as Ferroelectric Random Access read write Memory which enables a quite new function has been proposed.
High dielectric films (ferroelectric film) such as the above-mentioned Ta
2
O
5
, SrTiO
3
, Ba
X
Sr
1−X
TiO
3
(BST) and PbZr
X
Ti
1−X
O3 (PZT) are promising as a capacitor dielectric film. In general, the high dielectric films (ferroelectric film) are single or composite metal oxides.
However, it is difficult to use a polycrystalline silicon film, which has been conventionally used as a capacitor electrode, as the electrode for metal oxide dielectric. The reason is as follows. That is, in the case of using the polycrystalline silicon as the electrode, the surface of the polycrystalline silicon is oxidized during forming a capacitor metal oxide dielectric film; as a result, a silicon oxide is formed. The formed silicon oxide film functions as a layer having a low permittivity.
Thus, in the case of forming a capacitor of a large scale integrated circuit using the above mentioned high dielectric films (ferroelectric film), noble metals such as platinum and ruthenium. Because these noble metals are not oxidized even in an oxidizing ambient, or are still conductive even if they are oxidized.
For the micro-patterning of the noble metals, the following methods are employed. One is a method of forming a noble metal film by PVD or CVD method, and thereafter, carrying out micro-patterning by anisotropic etching such as RIE and the like. Another is a method of filling a noble metal film in a micro cavity used as a template, and thereafter, patterning the noble metal by a CMP method.
However, the noble metal has a low chemical reactivity and has a low adhesion with a substrate; for this reason, there is a problem such that it is hard to pattern the noble metal according to any of the above methods. In particular, materials such Ta
2
O
5
and Al
2
O
3
with a high permittivity of about 30 to 40 are amorphous and used as a capacitor dielectric film. In this case, in order to maximize a capacitor effective area while restricting a height of a capacitor cell, it is indispensable to employ a cylinder structure using both sides of a cylindrical electrode. Moreover, in the case of using the above materials BST and PZT, it is difficult to obtain a desired stored charge density or remnant polarization by a planar capacitor. For this reason, there is a need of micro-patterning the noble metal electrode into at least pedestal shape. However, generally, the noble metal is chemically inactive, therefore there are various problems to form a cylindrical or pedestal shape electrodes.
Electroplating has been employed as the new noble metal forming method instead of normal PVD or CVD methods. Electroplating has the following merits. That is, the process temperature is low (usually, the same as room temperature), and in the case of making a selective growth by electroplating, it is almost no necessary to pattern the noble metal. Further, the electroplating is not a vacuum process; therefore, it is instrumentally easy to prevent metal contamination on the backside of substrate, the process cost is low, and further, the apparatus can be made compact.
The following technology has been proposed as the conventional technology of forming a cylindrical electrode by electroplating. A template layer is formed on a substrate. A cavity is formed in the template layer so that the surface of the cavity can be formed with a capacitor electrode. A noble metal film is grown on the entire surface of the substrate. This is the application of the conventional method, which has been widely and practically used in a copper interconnect forming process.
One example of the conventional will be described below with reference to
FIG. 9A
to FIG.
9
D. In this case, in the following conventional manufacturing method, only one step will be described below. The above one step is a step of forming a lower electrode on a contact plug buried and formed in a contact hole formed at an interlayer dielectric (insulating) film.
First, as shown in
FIG. 9A
, a silicon nitride film
909
and a silicon oxide film
910
are sequentially formed on an interlayer dielectric film
107
and a contact plug
108
so that a template layer can be formed. By the public-known lithography technology, the silicon nitride film
909
and the silicon oxide film
910
are patterned to form a cavity
911
in which a lower electrode is formed. A ruthenium film
912
, which will become a seed layer, is formed on the entire surface of the substrate by sputtering.
Then, as shown in
FIG. 9B
, a ruthenium film
913
is grown by electroplating using the ruthenium film
912
as a seed. Here, the deposition is stopped before the ruthenium film
913
is fully filled in the cavity
911
.
As shown in
FIG. 9C
, a photo-resist film
914
is buried in the cavity
911
. Then, CMP is carried out so that unnecessary ruthenium films
912
and
913
on the interlayer dielectric film can be removed.
As shown in
FIG. 9D
, the above photo-resist film
914
and the silicon oxide film
910
are removed, and thereby, a cylindrical capacitor lower electrode is formed.
Further, according to the manufacturing method, the ruthenium film
913
is fully buried in the cavity
911
, and thereafter, the CMP method is carried out so that the ruthenium film
913
on the silicon oxide film
910
and the silicon oxide film
910
can be removed, and thereby, a cylindrical lower electrode can be formed.
However, the above conventional manufacturing method has the following problems. That is, it is assumed that an aspect ratio of the cavity becomes 5 or more after 0.1-micron generation. In order to uniformly grow an electroplating film in the cavity, there is a need of forming the seed layer up to the bottom of the cavity. However, it is difficult to form a uniform seed layer on a sidewall of the cavity by sputtering. In order to form the uniform seed layer on the sidewall, a thicker sputtered film must be formed; as a result, it is difficult to make thin the thickness of a cylinder wall.
When the seed layer is formed over the cavity having a large aspect ratio by sputtering, the sidewall near the bottom of the cavity is almost not covered with the seed layer.
Further, the electroplating seed layer is formed on the entire surface of
Eguchi Kazuhiro
Inoue Fumihiko
Kiyotoshi Masahiro
Nakabayashi Masaaki
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Tsai Jey
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