Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-07-31
2004-12-21
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S435000, C438S595000
Reexamination Certificate
active
06833295
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device using an SOI (silicon on insulator) substrate.
2. Description of the Related Art
As mobile communication equipments appear, power saving has been recently a great problem in addition to conventional miniaturization in demand for development of the semiconductor device. An SOI technology draws attention against such background. In the SOI technology, a CMOS (complementary metal oxide semiconductor) device having high driving performance after deep sub-micron is formed on a silicon substrate in which a silicon film (an SOI film) is completely separated by an oxide film (a buried oxide film) to be piled. An advantage of an SOI device is, in addition to small junction capacitance, that a drain current value at a low gate voltage is superior in rising, that is, a subthreshold becomes near to an ideal S factor. In order to attain this characteristic, required fully depletion by thinning an SOI film. Thinning an SOI film is also advantageous from the viewpoint of restraining short channel effect due to shortening of gate length. Thinning an SOI film, however, simultaneously leads to higher resistance in a diffusion layer portion and instability of a process such as reduction of a margin for through of a buried oxide film in forming contact. Therefore, the thickness of an SOI film should be made thin only for a channel portion under a gate and thick for a diffusion layer portion, respectively.
In order to meet the above demand, disclosed in JP-A-2001-257357, for example, a semiconductor device in which a channel portion under a gate in an SOI film is only thinned and a method of manufacturing the above. An example of such method of manufacturing a semiconductor device will be described here, made with reference to drawings.
In a conventional method of manufacturing a semiconductor device, as shown in
FIG. 2A
, a semiconductor substrate
112
in which an SOI film
116
of 100 nm in thickness, for example, (a silicon film) is piled through a medium of a box oxide film
114
(a buried oxide film) (referred to as an SOI substrate
100
hereinafter) is first prepared, a thermal oxide film
118
of 10 nm, for example, is formed on the above SOI film
116
, and a nitride film
120
of 30 nm, for example, is further formed on the thermal oxide film
118
by means of a CVD method. A photolithography process and an etching process are then carried out to eliminate the thermal oxide film
118
and the nitride film
120
so that a portion to be a channel region of the SOI film
116
would be exposed, and an opening pattern
122
is formed.
Next, as shown in
FIG. 2B
, the thermal film
118
and the nitride film
120
are used as a mask to carry out a thermal oxidation process for an exposed portion of the SOI film
116
, and a thermal oxide film
126
equal to 100 nm, for example, is formed at the same time when a channel region of the SOI film
116
is thinned.
Then, as shown in
FIG. 2C
, a wet etching process using thermal phosphoric acid and hydrofluoric acid of 1%, for example, is carried out for 20 and 18 minutes, respectively, to eliminate the thermal films
118
and
126
and the nitride film
120
. Accordingly, the thickness of the SOI film
116
becomes different between its channel region and other regions (diffusion layer: source and drain regions) so as to be 50 nm and 95 nm, for example.
As shown in
FIG. 2D
, a thermal oxidation process is then carried out to form a gate oxide film (a gate insulation film)
128
of 10 nm, for example. A channel ion, a B ion, for example, is implanted in an interface between the SOI film
116
and the gate oxide film
128
by means of an ion implantation method to form a channel region
130
. After a poly-silicon is deposited over the gate oxide film
128
by means of a CVD method, for example, to form a poly-silicon film of 200 nm, for example, a photolithography process and an etching process are carried out to form a gate electrode
134
.
Arsenic is then ion-implanted in the SOI film
116
surrounding the gate electrode
134
under a condition of implantation angle of 30 degrees, 50 KeV and 5×10
15
ions/cm
2
, for example. After that, an activation annealing process is carried out at 1000 degrees centigrade, for example, so as to form a source region
136
and a drain region
138
as a diffusion layer so that they would self align. Ti, for example, is then sputtered on surfaces of the gate electrode
134
, the source region
136
and the drain region
138
so as to carry out a salicide process, so that a gate silicide region
134
a
, a source silicide region
136
a
and a drain silicide region
138
a
would be formed.
An FD (fully depletion) type of MOSFET (power metal oxide semiconductor field effect transistor) is thus formed on an SOI substrate
100
as a semiconductor device.
In the method of manufacturing a semiconductor device as described above, the SOI film
116
of a portion to be a channel region
130
is first thinned and the thermal oxide film
118
and the nitride film
120
used for a mask are then eliminated to form a gate electrode
134
. In the above method, however, accuracy in processing the SOI film
116
of the channel region
130
and the gate electrode
134
is determined in accordance with positioning accuracy of a photolithographic exposure equipment.
Therefore, in order to surely thin the SOI film
116
located under the gate electrode
134
, it is required to set a thin-film region of the SOI film
116
in advance at a size that twice the positioning accuracy of the exposure equipment is added to a preferred size of a channel region
130
. In the case of forming a transistor having a gate width of 0.5 &mgr;m, for example, the thin-film region of the SOI film
116
should be set at 0.9 &mgr;m when the positioning accuracy of an exposure equipment to be used is 0.2 &mgr;m.
This results in excess thinning of the SOI film
116
region other than the channel region
130
, which causes problems such as rise in resistance in the diffusion layer (source and drain regions), rise in resistance due to concentration of a current path, rise in resistance due to lack of a contacting area between silicon and silicide and occurrence of defect due to lack of silicon in the silicide process. Furthermore, the gate electrode would be in an off position in many cases since the gate electrode
134
is formed by means of the photolithography and etching processes again after the thermal oxide film
118
and the nitride film
120
, which are used as a mask, are eliminated.
On the other hand, in a method of manufacturing a semiconductor device disclosed in JP-A-2001-257357, an opening portion is provided in an insulation film formed on an SOI film. A surface of the SOI film exposed from the opening portion is oxidation-processed to be thinned so as to self-align, poly-silicon is further buried in the opening portion to form a film, and thereby, a gate electrode is formed so as to self-align. Thus, a gate electrode is formed without any problems due to excess thinning of an SOI film region other than a channel region and off position of a gate electrode as mentioned above.
In the above proposition, however, an etching process damages a gate oxide film since an insulation film is eliminated after filling poly-silicon in an opening portion provided in the insulation film to form a film, and thereby, a gate electrode. This causes a problem of deterioration of electric characteristic.
Therefore, a purpose of the invention is to solve the above-described conventional problems and to achieve the following object. That is to say, an object of the invention is to provide a method of manufacturing a semiconductor device capable of forming a gate electrode in fewer processes without any problems due to excess thinning of a silicon film region and off position of a gate electrode and without any damages to a gate insulation film (a gate oxide film) due to an etching process.
SUMMARY OF THE INVENTION
The above prob
Dang Phuc T.
Oki Electric Industry Co. Ltd.
Rabin & Berdo P.C.
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