Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-02-14
2004-10-26
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S160000, C438S175000, C438S486000, C438S487000
Reexamination Certificate
active
06808968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device using gettering technique. Particularly, the present invention relates to a method of manufacturing a semiconductor device using a crystalline semiconductor film fabricated through the addition of a metal element that catalyzes the crystallization of a semiconductor film.
In the present specification, the “semiconductor device” denotes devices in general that can function by utilizing semiconductor properties, and electro-optic devices, semiconductor circuits, and electronic equipment all are semiconductor devices.
2. Description of the Related Art
A thin film transistor (hereinafter referred to as a “TFT”) has been known as a typical semiconductor device including a semiconductor film having a crystalline structure (hereinafter referred to as a “crystalline semiconductor film”). The TFT has been receiving attention as a technique of forming an integrated circuit on an insulating substrate such as glass, and for example, a driving circuit-integrated liquid crystal display device is proceeding toward practical utilization. In the conventional technique, an amorphous semiconductor film formed by a plasma CVD method or a low pressure CVD method is subjected to a heat treatment or a laser annealing process (a technique of crystallizing a semiconductor film by laser beam irradiation) and thereby a crystalline semiconductor film is fabricated.
The crystalline semiconductor film thus fabricated is an aggregation of many crystal grains crystal orientation of which is oriented in arbitral direction and the crystal orientation cannot be controlled, which constitutes a factor restricting the characteristics of the TFT. With respect to such a problem, Japanese Patent Application Laid-open No. Hei 7-183540 discloses a technique of fabricating a crystalline semiconductor film through the addition of a metal element such as nickel that catalyzes the crystallization of a semiconductor film. This technique not only provides an effect of lowering the heating temperature required for the crystallization but also can improve the orientation of crystal grains into a single direction. The formation of a TFT with such a crystalline semiconductor film allows not only electron field-effect mobility to be improved but also a subthreshold coefficient (S-value) to be lowered and thus makes it possible to improve electric characteristics by leaps and bounds.
However, since the metal element that exerts a catalytic action is added, there are problems in that the metal element remains in the crystalline semiconductor film or at its surface to cause variations in characteristics of the device obtained, and the like. One example of the problems is a problem such that an Off-state current increases in the TFT and varies among individual devices. In other words, once the metal element that catalyzes crystallization is used to form a crystalline semiconductor film, it becomes rather an unwanted existence.
SUMMARY OF THE INVENTION
The present invention is intended to achieve the reduction in number of heat treatments carried out at high temperature (at least 600° C.) and the employment of lower temperature processes (600° C. or lower), and to achieve step simplification and throughput improvement.
A method of manufacturing a semiconductor device according to the present invention includes: a step of forming a first semiconductor film having a crystalline structure using a metal element; a step of forming a film (a barrier layer) to serve as an etching stopper; a step of forming a second semiconductor film; a step of forming a third semiconductor film (a gettering site) containing an impurity element that imparts one conductive type; a step of allowing the gettering site to getter the metal element; and a step of removing the second semiconductor film and the third semiconductor film.
The impurity element that imparts one conductive type to the semiconductor is one selected from the group consisting of elements belonging to Group 15 or 13 in the periodic table. Typical elements of elements belonging to Group 15 in the periodic table are phosphorus (P) and arsenic (As), and a typical element of elements belonging to Group 13 in the periodic table is boron (B).
The step of forming a third semiconductor film (a gettering site) containing an impurity element that imparts one conductive type may be carried out by the plasma CVD method or a low pressure thermal CVD method using a raw material gas containing an impurity element that imparts one conductive type. In this case, however, it is necessary to adjust film formation conditions so as to prevent the third semiconductor film from being peeled off. As another method, after a semiconductor film having an amorphous structure or a crystalline structure is formed, an impurity element that imparts one conductive type to the semiconductor film may be added to form the third semiconductor film. In addition, an ion doping process or an ion implantation process may be employed as the method for adding the impurity element that imparts one conductive type. As still another method, the third semiconductor film may be formed by sputtering technique using a target containing an impurity element that imparts one conductive type.
In addition to the impurity element that imparts one conductive type, one element or more selected from the group consisting of H, H
2
, O, O
2
, and rare gas elements may be added. The addition of a plurality of elements allows a gettering effect to be obtained synergistically. Of those, O and O
2
are effective, and gettering efficiency is improved when the oxygen concentration, which is determined by a secondary ion mass spectroscopy (SIMS) analysis, in the second or third semiconductor film is set to be at least 5×10
18
/cm
3
, preferably in the range of 1×10
19
/cm
3
to 1×10
22
/cm
3
as a film formation condition or by the addition of O or O
2
after film formation.
Since the impurity element that imparts one conductive type tends to diffuse, it is preferable to prevent the impurity element from diffusing into the first semiconductor film due to the heat treatment to be carried out later by controlling the thickness of the second semiconductor film. Besides the second semiconductor film, the barrier layer also has a function of preventing the diffusion. In this case, however, it is necessary to adjust the film formation conditions so as to prevent the second semiconductor film from being peeled off. For instance, when the second semiconductor film is formed by the plasma CVD method, it is preferable to form it by RF continuous oscillation under the conditions that allow tensile stress to be produced. When an amorphous silicon film is formed to have a thickness of 200 nm using silane gas (SiH
4
: with a flow rate of 100 sccm) as a film formation gas at an RF power of 35 W under a film formation pressure of 0.25 Torr, the tensile stress is about 1.12×10
9
(dynes/cm
2
). As a comparative example, when an amorphous silicon film is formed by RF pulsed oscillation, the film may exert compressive stress (about −9.7×10
9
(dynes/cm
2
)) and thus may be peeled off.
Generally, the internal stress includes tensile stress and compressive stress. When a thin film formed on a substrate is going to shrink, the substrate pulls the thin film in the directions that prevent its shrinkage and thereby is deformed to make the thin film locate on the inner side. This is called “tensile stress”. On the other hand, when the thin film is going to expand, the substrate is forced to be compressed and thereby is deformed to make the thin film locate on the outer side. This is called “compressive stress”.
A first structure of the present invention disclosed in this specification relates to a method of manufacturing a semiconductor device, comprising: a first step of adding a metal element to a first semiconductor film having an amorphous structure; a second step of crystallizing the first semiconductor film
Asami Taketomi
Dairiki Koji
Ichijo Mitsuhiro
Kajiwara Masayuki
Koezuka Junichi
Le Dung A.
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
LandOfFree
Method of manufacturing a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3290909