Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-17
2004-03-09
Graybill, David E. (Department: 2827)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000, C438S425000, C438S426000, C438S424000, C438S435000, C438S437000, C438S692000, C438S697000
Reexamination Certificate
active
06703270
ABSTRACT:
The invention relates to a method of manufacturing a semiconductor device, comprising the steps of:
forming a patterned masking layer of insulating material at a surface of a semiconductor body,
etching the semiconductor body through the patterned masking layer so as to form a trench in the semiconductor body,
applying an insulating layer which fills the trench in the semiconductor body, the insulating layer exhibiting a trough above the trench, which trough has a bottom area lying substantially above the surface of the semiconductor body,
subjecting the semiconductor body to a planarizing treatment so as to form a substantially planar surface,
subjecting the semiconductor body to a further treatment so as to expose the semiconductor body and form a field isolating region.
Such a method is known from EP-A-0 461 498. In the known method the patterned masking layer comprises a stop layer, which stop layer is formed of, for example, CVD silicon nitride. After formation of the trench and application of the insulating layer, which insulating layer is formed of, for example, CVD silicon oxide, the semiconductor body is subjected to a planarizing treatment, wherein the surface of the insulating layer is polished with a chemical mechanical polisher having a soft semirigid pad saturated with a slurry of abrasive particles such as colloidal silica in an alkaline base and water. The saturated pad is used to rub on the surface of the insulating layer to perform chemical mechanical polishing and erode the insulating layer. The stop layer is adapted to erode much more slowly than the insulating layer. Therefore, when polishing gets to the level of the stop layer, polishing is slowed down. The planarization of the insulating layer is thus provided with a self-stopping feature.
A disadvantage of the known method is that a stop layer formed of, for example, silicon nitride has to be applied for slowing down the planarization of the insulating layer. Such a stop layer is usually removed in a dirty and expensive process step such as, for example, a wet etch step using hot phosphoric acid.
The invention has for its object inter alia to provide a method of manufacturing a semiconductor device of the kind mentioned in the opening paragraph, which method makes it possible to circumvent the application of a stop layer for the planarization of the insulating layer used for trench filling.
According to the invention, this object is achieved in that the insulating layer is removed substantially to the bottom area of the trough by means of chemical mechanical polishing using fixed abrasives during the planarizing treatment. By applying chemical mechanical polishing (CMP) using fixed abrasives, in which CMP technique the abrasive particles are embedded in the polishing pad, instead of conventional CMP, which is carried out using an abrasive slurry combined with a polishing pad, the removal rate at top areas of features is higher while the removal rate at bottom areas of features is much lower. The removal rate at bottom areas of features is even very low when applying CMP using fixed abrasives. Clearly, the faster step height reduction and very low removal rate at bottom areas, which are obtainable by applying CMP using fixed abrasives, make it possible to circumvent the use of a stop layer. When the polishing gets to the bottom areas of the features, the polishing is automatically slowed down.
A preferred embodiment of the method in accordance with the invention is characterized in that
the patterned masking layer is left at the surface of the semiconductor body after formation of the trench,
the patterned masking layer is formed of a material with respect to which the insulating layer is not substantially selectively removable during the planarizing treatment. In this way, the surface of the semiconductor body is protected by the patterned masking layer against contamination during subsequent process steps, which patterned masking layer does not act as a stop layer during the planarizing treatment.
In order to easily adjust the extent to which the field isolating region rises above the surface of the semiconductor body, it is advantageous that
the patterned masking layer is removed over at most a part of its thickness during the planarizing treatment,
the patterned masking layer is etched much faster than the insulating layer during the further treatment.
Further advantageous embodiments of the method in accordance with the invention are described in the other dependent claims.
REFERENCES:
patent: 5837612 (1998-11-01), Ajuria et al.
patent: 6039631 (2000-03-01), Sato et al.
patent: 0461498 (1991-12-01), None
patent: 0961315 (1999-12-01), None
Knotter Dirk Maarten
Van Der Velden Peter
Graybill David E.
Koninklijke Philips Electronics , N.V.
Waxoer Aaron
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